TC1272A

DS21877A-page 4

 2004 Microchip Technology Inc.

3.0

APPLICATIONS INFORMATION

3.1

reset timing during power-up, power-down and brown-

out/sag conditions. These devices also reject negative-

going transients (glitches) on the power supply line.

Figure 3-1 shows the maximum transient duration vs.

maximum negative excursion (overdrive) for glitch

rejection. Any combination of duration and overdrive

that lies under the curve will not generate a reset

signal.

FIGURE 3-1:

Maximum Transient

Duration vs. Overdrive for Glitch Rejection at

+25°C.

Combinations above the curve are detected as a

brown-out or power-down condition. Transient immu-

nity can be improved by adding a capacitor in close

3.2

RESET Signal Integrity During

Power-Down

Below this voltage, the output becomes an "open cir-

cuit" and does not sink current. This means CMOS

logic inputs to the microcontroller will be floating at an

undetermined voltage. Most digital systems are com-

pletely shut down well above this voltage. However, in

situations where RESET must be maintained valid to

RESET to ground to discharge stray capacitances and

hold the output low (Figure 3-2). This resistor value,

though not critical, should be chosen such that it does

not appreciably load RESET under normal operation

(100 k

Ω will be suitable for most applications).

FIGURE 3-2:

RESET output of the TC1272A ensures that the

Reset Comparator Overdrive

[V

400

240

160

320

80

0

1

5

100

1000

T

V

TH

Duration

Overdrive

V

DD

TC1272A/L/M/J

TC1272A/Z/R/S/T

[V

30

40

50

60

70

80

90

100

110

120

130

1

10

100

1000

Reset Comparator Overdrive (mV)

TC1272A/L/M/J

TC1272A/Z/R/S/T

TC1272A

V

DD

V

DD

100 k

Ω

RESET

GND