AD9203 datasheet(13/28 Pages) AD

13 / 28 page

AD9203

0.1

µF

Rev. B | Page 13 of 28

ADC

CORE

–

LOGIC

AINP

AINN

VREF

0.5V

REFTF

REFBF

REFSENSE

1.5V

1.875V

1.125V

AD9203

0.1

µF

0.1

µF

0.1

µF

Figure 21. Programmable Reference Configuration

EXTERNAL REFERENCE OPERATION

Figure 22 illustrates the use of an external reference. An

external reference may be necessary for several reasons. Tighter

reference tolerance will enhance the accuracy of the ADC and

will allow lower temperature drift performance. When several

ADCs track one another, a single reference (internal or

external) will be necessary. The AD9203 will draw less power

when an external reference is used.

When the REFSENSE pin is tied to AVDD, the internal

reference will be disabled, allowing the use of an external

reference.

The AD9203 contains an internal reference buffer. It will load

the external reference with an equivalent 10 kΩ load. The

internal buffer will generate positive and negative full-scale

references for the ADC core.

In Figure 22, an external reference is used to set the midscale set

point for single-ended use. At the same time, it sets the input

voltage span through a resistor divider. If the ADC is being

driven differentially through a transformer, the external

reference can set the center tap (common-mode voltage).

µF

0.1

µF

0.1

µF

0.1

µF

1.0V

2.0V

VREF

AD9203

1.5k

Ω

3.0V

REFSENSE

AVDD

AINP

AINN

EXTERNAL

REF (2V)

1.5k

Ω

Figure 22. External Reference Configuration

CLAMP OPERATION

The AD9203 contains an internal clamp. It may be used when

operating the input in a single-ended mode. This clamp is very

useful for clamping NTSC and PAL video signals to ground.

The clamp cannot be used in the differential input mode.

1V p-p

0V DC

REFSENSE

VREF

AINN

CIN

CLAMPIN

CLAMP

AD9203

AINP

SW1

Ω TYP

ADC

CORE

Figure 23. Clamp Configuration (VREF = 0.5 V)

Figure 23 shows the internal clamp circuitry and the external

control signals needed for clamp operation. To enable the

clamp, apply a logic high 1 to the CLAMP pin. This will close

SW1, the internal switch. SW1 is opened by asserting the

CLAMP pin low 0. The capacitor holds the voltage across CIN

constant until the next interval. The charge on the capacitor will

leak off as a function of input bias current (see Figure 24).

–50

250

200

150

100

0.5

1.0

1.5

2.0

2.5

3.0

INPUT VOLTAGE (V)

Figure 24. Input Bias Current vs. Input Voltage (FS = 40 MSPS)

DRIVING THE ANALOG INPUT

Figure 25 illustrates the equivalent analog input of the AD9203,

(a switched capacitor input). Bringing CLK to a logic high,

opens S3 and closes S1 and S2. The input source connected to

AIN and must charge Capacitor CH during this time. Bringing

CLK to a logic low opens S2, and then S1 opens followed by

closing S3. This puts the input in the hold mode.

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