AM186 datasheet(38/112 Pages) AMD

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Am186TMER and Am188TMER Microcontrollers Data Sheet

DRAF

SRDY/PIO6

Synchronous Ready (input, synchronous,

level-sensitive)

This pin indicates to the microcontroller that the ad-

dressed memory space or I/O device will complete a

data transfer. The SRDY pin accepts an active High

input synchronized to CLKOUTA.

Using SRDY instead of ARDY allows a relaxed system

timing because of the elimination of the one-half clock

period required to internally synchronize ARDY. To al-

ways assert the ready condition to the microcontroller,

tie SRDY High. If the system does not use SRDY, tie the

pin Low to yield control to ARDY. When SRDY is config-

ured as P106, the internal SRDY signal is driven low.

TMRIN0/PIO11

Timer Input 0 (input, synchronous, edge-sensitive)

This pin supplies a clock or control signal to the internal

microcontroller timer 0. After internally synchronizing a

Low-to-High transition on TMRIN0, the microcontroller

increments the timer. TMRIN0 must be tied High if not

being used.

TMRIN1/PIO0

Timer Input 1 (input, synchronous, edge-sensitive)

This pin supplies a clock or control signal to the internal

microcontroller timer 1. After internally synchronizing a

Low-to-High transition on TMRIN1, the microcontroller

increments the timer. TMRIN1 must be tied High if not

being used.

TMROUT0/PIO10

Timer Output 0 (output, synchronous)

This pin supplies the system with either a single pulse

or a continuous waveform with a programmable duty

cycle.

TMROUT1/PIO1

Timer Output 1 (output, synchronous)

This pin supplies the system with either a single pulse

or a continuous waveform with a programmable duty

cycle.

TXD/PIO27

Transmit Data (output, asynchronous)

This pin supplies asynchronous serial transmit data to

the system from the internal UART of the microcontrol-

ler.

UCS/ONCE1

Upper Memory Chip Select (output, synchronous)

ONCE Mode Request 1 (input, internal pullup)

UCS—This pin indicates to the system that a memory

access is in progress to the upper memory block. The

base address and size of the upper memory block are

programmable up to 512 Kbyte. UCS is held High dur-

ing a bus hold condition.

After power-on reset, UCS is asserted because the mi-

crocontroller begins executing at FFFF0h and the de-

fault configuration for the UCS chip select is 64 Kbyte

from F0000h to FFFFFh.

ONCE1—During reset, this pin and ONCE0 indicate to

the microcontroller the mode in which it should operate.

ONCE0 and ONCE1 are sampled on the rising edge of

RES. If both pins are asserted Low, the microcontroller

enters ONCE mode. Otherwise, it operates normally. In

ONCE mode, all pins assume a high-impedance state

and remain in that state until a subsequent reset oc-

curs. To guarantee the microcontroller does not inad-

vertently enter ONCE mode, ONCE1 has a weak

internal pullup resistor that is active only during a reset.

UZI/CLKSEL2/PIO26

Upper Zero Indicate (output, synchronous)

UZI—This pin lets the designer determine if an ac-

cess to the interrupt vector table is in progress by

ORing it with bits 15–10 of the address and data bus

(AD15–AD10 on the Am186ER microcontroller and

AO15–AO10 on the Am188ER microcontroller). UZI

is the logical AND of the inverted A19–A16 bits. UZI

is not held throughout the cycle. UZI is asserted in

the first period and deasserted in the second period

of a bus cycle. UZI/CLKSEL2 is three-stated during

bus holds and ONCE mode.

CLKSEL2—The clocking mode of the Am186ER and

Am188ER microcontrollers is controlled by UZI/

CLKSEL2/PIO26 and S6/CLKSEL1/PIO29 during re-

set. Both CLKSEL2 and CLKSEL1 are held High during

power-on reset because of an internal pullup resistor.

This is the default clocking mode—Times Four, which

is used if neither clock select is asserted Low during re-

set.

If CLKSEL2 is held Low during power-on reset, the mi-

crocontroller enters Times One mode.

This pin is latched within three crystal clock cycles after

the rising edge of RES. Refer to Reset Waveforms on

page 100 and Signals Related to Reset Waveforms on

page 100 to determine signal hold times. Note that

clock selection must be stable four clock cycles prior to

exiting reset (that is, RES going High). See Table 6 on

page 39 for specifics on the clocking modes and how to

specify them. UZI/CLKSEL2 is three-stated during bus

holds and ONCE mode.

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