AD7859AP datasheet(23/28 Pages) AD

23 / 28 page

AD7859/AD7859L

REV. A

–23–

System Gain and Offset Interaction

The architecture of the AD7859/AD7859L leads to an interac-

tion between the system offset and gain errors when a system

calibration is performed. Therefore, it is recommended to per-

form the cycle of a system offset calibration followed by a sys-

tem gain calibration twice. When a system offset calibration is

performed, the system offset error is reduced to zero. If this is

followed by a system gain calibration, then the system gain error

is now zero, but the system offset error is no longer zero. A sec-

ond sequence of system offset error calibration followed by a

system gain calibration is necessary to reduce system offset error

to below the 12-bit level. The advantage of doing separate

system offset and system gain calibrations is that the user has

more control over when the analog inputs need to be at the

required levels, and the CONVST signal does not have to be

used.

Alternatively, a system (gain + offset) calibration can be per-

formed. At the end of one system (gain + offset) calibration, the

system offset error is zero, while the system gain error is reduced

from its initial value. Three system (gain + offset) calibrations

are required to reduce the system gain error to below the 12-bit

error level. There is never any need to perform more than three

system (gain + offset) calibrations.

In bipolar mode the midscale error is adjusted for an offset cali-

bration and the positive full-scale error is adjusted for the gain

calibration; in unipolar mode the zero-scale error is adjusted for

an offset calibration and the positive full-scale error is adjusted

for a gain calibration.

System Calibration Timing

The timing diagram in Figure 33 is for a software full system

calibration. It may be easier in some applications to perform

separate gain and offset calibrations so that the CONVST bit in

the control register does not have to be programmed in the

middle of the system calibration sequence. Once the write to the

control register setting the bits for a full system calibration is

completed, calibration of the internal DAC is initiated and the

BUSY line goes high. The full-scale system voltage should be

applied to the analog input pins, AIN(+) and AIN(–) at the start

of calibration. The BUSY line goes low once the DAC and sys-

tem gain calibration are complete. Next the system offset volt-

age should be applied across the AIN(+) and AIN(–) pins for a

minimum setup time (tSETUP) of 100 ns before the rising edge of

. This second write to the control register sets the CONVST

bit to 1 and at the end of this write operation the BUSY signal is

triggered high (note that a CONVST pulse can be applied in-

stead of this second write to the control register). The BUSY

signal is low after a time tCAL2 when the system offset calibration

section is complete. The full system calibration is now complete.

The timing for a system (gain + offset) calibration is very similar

to that of Figure 33, the only difference being that the time

tCAL1 is replaced by a shorter time of the order of tCAL2 as the in-

ternal DAC is not calibrated. The BUSY signal signifies when

the gain calibration is finished and when the part is ready for the

offset calibration.

t19

DATA LATCHED INTO

CONTROL REGISTER

HI-Z

t19

tSETUP

DATA

VALID

tCAL1

tCAL2

VOFFSET

CONVST BIT SET TO 1 IN

CONTROL REGISTER

DATA

BUSY

AIN

DATA

VALID

VSYSTEM FULL SCALE

Figure 33. Timing Diagram for Full System Calibration

The timing diagram for a system offset or system gain calibra-

tion is shown in Figure 34. Here again a write to the control reg-

ister initiates the calibration sequence. At the end of the control

high until the calibration sequence is finished. The analog input

should be set at the correct level for a minimum setup time

(tSETUP) of 100 ns before the CS rising edge and stay at the cor-

rect level until the BUSY signal goes low.

t19

HI-Z

DATA LATCHED INTO

CONTROL REGISTER

tSETUP

BUSY

AIN

DATA

VALID

tCAL2

VSYSTEM FULL SCALE OR VOFFSET

Figure 34. Timing Diagram for System Gain or

System Offset Calibration

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