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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AGLP060 датащи(PDF) 83 Page - Microsemi Corporation |
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AGLP060 датащи(HTML) 83 Page - Microsemi Corporation |
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83 / 134 page  IGLOO PLUS Low Power Flash FPGAs Revision 16 2-69 Table 2-93 • RAM512X18 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tAS Address setup time 0.69 ns tAH Address hold time 0.13 ns tENS REN, WEN setup time 0.61 ns tENH REN, WEN hold time 0.07 ns tDS Input data (WD) setup time 0.59 ns tDH Input data (WD) hold time 0.30 ns tCKQ1 Clock High to new data valid on RD (output retained) 3.51 ns tCKQ2 Clock High to new data valid on RD (pipelined) 1.43 ns tC2CRWH1 Address collision clk-to-clk delay for reliable read access after write on same address – applicable to opening edge 0.21 ns tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same address – applicable to opening edge 0.25 ns tRSTBQ RESET Low to data out Low on RD (flow-through) 1.72 ns RESET Low to data out Low on RD (pipelined) 1.72 ns tREMRSTB RESET removal 0.51 ns tRECRSTB RESET recovery 2.68 ns tMPWRSTB RESET minimum pulse width 0.68 ns tCYC Clock cycle time 6.24 ns FMAX Maximum frequency 160 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. |
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