FG256 datasheet(21/162 Pages) MICROSEMI

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ProASIC3E Flash Family FPGAs

Revision 13

2-7

HSTL (I)

1.5

0.17

2.03

HSTL (II)

1.5

0.17

2.03

SSTL2 (I)

2.5

1.38

4.48

SSTL2 (II)

2.5

1.38

4.48

SSTL3 (I)

3.3

3.21

9.26

SSTL3 (II)

3.3

3.21

9.26

Differential

LVDS/B-LVDS/M-LVDS

2.5

2.26

1.50

LVPECL

3.3

5.71

2.17

Table 2-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1

CLOAD

(pF)

VCCI

(V)

Static Power

PDC3 (mW)2

Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL/LVCMOS

3.3

–

474.70

3.3 V LVTTL/LVCMOS Wide Range4

3.3

–

474.70

2.5 V LVCMOS

2.5

–

270.73

1.8 V LVCMOS

1.8

–

151.78

1.5 V LVCMOS (JESD8-11)

1.5

–

104.55

3.3 V PCI

3.3

–

204.61

3.3 V PCI-X

3.3

–

204.61

Voltage-Referenced

3.3 V GTL

3.3

–

24.08

2.5 V GTL

2.5

–

13.52

3.3 V GTL+

3.3

–

24.10

2.5 V GTL+

2.5

–

13.54

HSTL (I)

1.5

7.08

26.22

HSTL (II)

1.5

13.88

27.22

SSTL2 (I)

2.5

16.69

105.56

SSTL2 (II)

2.5

25.91

116.60

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC3 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCC and VCCI.

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings (continued)

VMV

(V)

Static Power

PDC2 (mW)1

Dynamic Power

PAC9 (µW/MHz)2

Notes:

1. PDC2 is the static power (where applicable) measured on VMV.

2. PAC9 is the total dynamic power measured on VCC and VMV.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.

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