MP8762GL datasheet(18/39 Pages) MPS

18 / 39 page

MP8762 ― 10A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER

MP8762 Rev. 1.4

www.MonolithicPower.com

11/4/2013

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

APPLICATION INFORMATION

Setting the Output Voltage-Large ESR Caps

For applications that electrolytic capacitor or POS

capacitor with a controlled output of ESR is set

as output capacitors. The output voltage is set by

feedback resistors R1 and R2. As figure 10

shows.

ESR

POSCAP

VOUT

Figure10—Simplified Circuit of POS Capacitor

First, choose a value for R2. R2 should be

chosen reasonably, a small R2 will lead to

considerable quiescent current loss while too

large R2 makes the FB noise sensitive. It is

recommended to choose a value within 5kΩ-

50kΩ for R2, using a comparatively larger R2

when VOUT is low, and a smaller R2 when VOUT is

high. Then R1 is determined as follow with the

output ripple considered:

OUT

REF

−× Δ

−

=×

(15)

OUT

is the output ripple determined by equation

24.

Setting the Output Voltage-Small ESR Caps

Ceramic

VOUT

Figure11—Simplified Circuit of Ceramic

Capacitor

When low ESR ceramic capacitor is used in the

output, an external voltage ramp should be

added to FB through resistor R4 and capacitor

C4.The output voltage is influenced by ramp

voltage VRAMP besides resistor divider as shown

in figure 11. The VRAMP can be calculated as

shown in equation 7. R2 should be chosen

reasonably, a small R2 will lead to considerable

quiescent current loss while too large R2 makes

the FB noise sensitive. It is recommended to

choose a value within 5kΩ-50kΩ for R2, using a

comparatively larger R2 when VOUT is low, and a

smaller R2 when VOUT is high. And the value of

R1 then is determined as follow:

)

AVG

(

OUT

)

AVG

(

−

(16)

The VFB(AVG) is the average value on the FB.

VFB(AVG) varies with the VIN, VOUT, and load

condition, etc.. Its value on the skip mode would

be lower than that of the PWM mode, which

means the load regulation is strictly related to the

VFB(AVG). Also the line regulation is related to the

VFB(AVG) ,if one wants to gets a better load or line

regulation, a lower VRAMP is suggested once it

meets equation 9.

For PWM operation, VFB(AVG) value can be

deduced from equation 17.

RAMP

REF

)

AVG

(

(17)

Usually, R9 is set to 0Ω, and it can also be set

following equation 18 for a better noise immunity.

It also should be set to be 5 timers smaller than

R1//R2 to minimize its influence on VRAMP.

1R1 R2

5R1 R2

<×

(18)

Using equation 16 and 17 to calculate the output

voltage can be complicated. To simplify the

calculation of R1 in equation 11, a DC-blocking

capacitor CDC can be added to filter the DC

influence from R4 and R9. Figure 12 shows a

simplified

circuit

with

external

ramp

compensation and a DC-blocking capacitor. With

this capacitor, R1 can easily be obtained by

using equation 19 for PWM mode operation.

MP8762GL датащи(PDF) 18 Page - Monolithic Power Systems

MP8762GL датащи(HTML) 18 Page - Monolithic Power Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

датащи скачать

ссылки URL