MP4651—OFF LINE LED DRIVER

MP4651 Rev.1.0

www.MonolithicPower.com

11

1/13/2011

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rise

BFS

Burst

BFS

1D

C

f

R

0.405

−

=

××

52nF

For direct PWM burst dimming, pull BFS high to

VCC through a 20kΩ resistor and apply the PWM

signal to PWMIN pin.

Pin 2 (SYNC):

Burst frequency synchronization. This pin is used

to synchronize the burst dimming frequency.

Applying a synchronizing frequency signal with

small pulse will synchronize the burst frequency.

SYNC

EN

FB

VCC

BFS

FSET

FT

GND

GL

PWMOUT

VIN

GR

OVP

PWMIN

COMP

1

2

3

4

5

6

7

8

MP4651

14

15

16

SSD

10

11

12

SYNC

Signal

9

REF

13

A

BFS

Burst dimming

signal

1.2V

3.55V

2.4V

SYNC

Signal

A

Figure 4—Synchronized DC Input Burst

Dimming

Figure 4 shows the synchronized DC input burst

dimming. The synchronizing signal is filtered by

a high pass filter. Its rising edge is caught and

used for synchronizing the triangle waveform on

BFS pin. The synchronizing frequency should be

higher than that set by BFS pin and the

amplitude of the synchronizing signal should be

higher than 1.4V.

Table 1—Function Mode

Function

Pin Connection

PWM

BFS

SYNC

Burst Mode with DC

Input Voltage

0V to

1.2V

GND

Burst Mode with DC

Input Voltage and

Synchronizing

frequency

0V to

1.2V

R,C,D

network

Burst Mode with

External PWM Source

PWM

To VCC

through

20kΩ

resistor

GND

Burst Brightness Polarity: 100% duty cycle at

PWM voltage 1.2V.

Pin 11 (EN):

Pull this pin high to enable the chip, and pull it

low to disable the chip.

Pin 12 (VIN):

Supply voltage input. Bypass the supply voltage

with a 0.1uF or greater ceramic cap. This cap

should be placed close to the IC.

Pin 13 (VCC):

This pin provides the gate driver supply voltage,

its typical value is 9.7V. Connect a 1uF or greater

ceramic capacitor on this pin to bypass the

supply voltage. This voltage is also used to

supply the external control circuit.

Pin 14(GL), Pin 16 (GR):

Gate driving signals output. GL and GR are 180

degree phase shifted driving signals. With its

enhanced driving capability, GL and GR are able

to directly drive the externally MOSFET in the off-

line system through a gate driving transformer.

Connect two 5Ω resistors in series with GL and

GR to reduce the EMI noise.

A 2.2nF Y capacitor is recommended to be

placed between the primary reference ground

and secondary reference ground.