MP2633 – 1.5A SINGLE CELL SWITCH MODE BATTERY CHARGER

MP2633 Rev. 1.05

www.MonolithicPower.com

30

4/19/2013

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L

f

C

8

V

/

V

1

V

V

r

2

S

BATT

SYS

BATT

BATT

BATT

BATT

×

×

×

−

=

Δ

=

Δ

(29)

2.

Boost Mode

the boost converter. The input voltage ripple

is the same as the output voltage ripple from

equation (29).

Both charge mode and boost mode have the

can be calculated as:

L

f

r

8

V

/

V

1

C

2

S

MAX

_

BATT

MAX

_

SYS

TC

BATT

×

×

Δ

×

−

=

(30)

To guarantee the ±0.5% BATT voltage accuracy,

the maximum BATT voltage ripple must not

exceed 0.5% (e.g., 0.1%). The worst case occurs

at the minimum battery voltage of the CC charge

with the maximum input voltage.

%

1

.

0

r

MAX

_

BATT

=

Δ

22µF (for a 600kHz switching frequency) or 10µF

(for a 1.2MHz switching frequency).

A 22µF ceramic with X5R or X7R dielectrics

capacitor in parallel with a 220uF electrolytic

capacitor will suffice.

PCB LAYOUT GUIDE

PCB layout is very important to meet specified

noise, efficiency and stability requirements. The

following design considerations can improve

circuit performance:

1) Route the power stage adjacent to their

grounds. Aim to minimize the high-side switching

node (SW, inductor) trace lengths in the high-

current paths and the current sense resistor trace.

Keep the switching node short and away from all

small control signals, especially the feedback

network.

Place the input capacitor as close as possible to

the VIN and PGND pins. The local power input

capacitors, connected from the SYS to PGND,

must be placed as close as possible to the IC.

Place the output inductor close to the IC and

connect the output capacitor between the

inductor and PGND of the IC.

2) For high-current applications, the power pads

for IN, SYS, SW, BATT and PGND should be

connected to as many copper planes on the

board as possible. The exposed pad should

connect to as many GND copper planes in the

board as possible. This improves thermal

performance because the board conducts heat

away from the IC.

3) The PCB should have a ground plane

connected directly to the return of all components

through vias (e.g., two vias per capacitor for

power-stage capacitors, one via per capacitor for

small-signal components). If possible, add vias

inside the exposed pads for the IC. A star ground

design approach is typically used to keep circuit

block currents isolated (power-signal/control-

signal),

which

reduces

noise-coupling

and

ground-bounce issues. A single ground plane for

this design gives good results.

4) Place ISET, OLIM and ILIM resistors very

close to their respective IC pins.

Top Layer

Bottom Layer

Figure 13 PCB Layout Guide