STR83145

LATCHED, UNIVERSAL

INPUT-VOLTAGE SWITCH

www.allegromicro.com

3

SIMPLIFIED OPERATION

(unless otherwise noted).

Limits

Characteristic

Symbol

Test Conditions

Min.

Typ. Max.

Units

On-State Voltage

V

TM

I

–

–

1.8

V

Off-State Current

I

DRM

V

–

–

100

µA

Starting Voltage

V

S

V

–

–

100

V

Startup Time Delay

t

D

C

40

–

100

ms

DC Switch-Over Voltage

V

C

V

200

205

210

V

Temperature Coefficient

of Switch-Over Voltage

α

VC

-20

°C ≤ T

±45

–

mV/

°C

Input Current

I

MT1

Voltage-doubler mode, V

–

–

10

mA

Full-bridge mode, V

–

–

6.5

mA

Delay Terminal Voltage

V

DELAY

––

7.0

V

Triac Gate-Drive Osc. Freq.

f

o

V

–

15

–

kHz

Latch Reset Voltage

V

R

V

2.0

–

15

V

Thermal Resistance

FET channel to mounting surface

–

–

1.8

°C/W

NOTES: Negative current is defined as coming out of (sourcing) the specified device terminal.

Typical Data is for design information only.

+

+

240–373 V peak

+

+

246–373 V peak

Full-Bridge Mode

Dwg. EK-006

Voltage-Doubler Mode