LM77 datasheet(5/23 Pages) TI

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LM77

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SNIS103F – JUNE 1999 – REVISED MARCH 2013

Logic Electrical Characteristics Digital DC Characteristics (continued)

Unless otherwise noted, these specifications apply for +VS=+5 Vdc ±10% for LM77CIM-5, LM77CIMM-5 and +VS=+3.3 Vdc

±10% for LM77CIM-3, LM77CIMM-3. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA= TJ=+25°C, unless

otherwise noted.

Units

Parameter

Test Conditions

Typical(1)

Limits(2)

(Limit)

VOL

Low Level Output Voltage

IOL = 3 mA

0.4

V (max)

T_CRIT_A Output Saturation Voltage

IOUT = 4.0 mA

(3)

0.8

V (max)

T_CRIT_A Delay

Conversions

(max)

tOF

Output Fall Time

CL = 400 pF

250

ns (max)

IO = 3 mA

(3)

For best accuracy, minimize output loading. Higher sink currents can affect sensor accuracy with internal heating. This can cause an

error of 0.64°C at full rated sink current and saturation voltage based on junction-to-ambient thermal resistance.

Logic Electrical Characteristics Serial Bus Digital Switching Characteristics

Unless otherwise noted, these specifications apply for +VS=+5 Vdc ±10% for LM77CIM-5 and LM77CIMM-5, +VS=+3.3 Vdc

±10% for LM77CIM-3 and LM77CIMM-3, CL (load capacitance) on output lines = 80 pF unless otherwise specified. Boldface

limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C, unless otherwise noted.

Units

Parameter

Test Conditions

Typical(1)

Limits(2)(3)

(Limit)

SCL (Clock) Period

2.5

μs(min)

Data in Set-Up Time to SCL High

100

ns(min)

Data Out Stable after SCL Low

ns(min)

SDA Low Set-Up Time to SCL Low (Start Condition)

100

ns(min)

SDA High Hold Time after SCL High (Stop Condition)

100

ns(min)

(1)

Typicals are at TA = 25°C and represent most likely parametric norm.

(2)

Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).

(3)

Timing specifications are tested at the bus input logic levels (Vin(0)=0.3xVA for a falling edge and Vin(1)=0.7xVA for a rising edge) when

the SCL and SDA edge rates are similar.

Figure 4.

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