MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

MP1492 Rev. 1.1

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14

3/13/2012

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should also not larger than 0.47μF considering

start up performance. In case one wants to use a

larger Cdc for a better FB noise immunity,

combined with reducing R1 and R2 to limit the

Cdc in a reasonable value without affecting the

system start up. Be noted that even when the

Cdc is applied, the load and line regulation are

still Vramp related.

Figure10—Simplified Circuit of Ceramic

Capacitor with DC blocking capacitor

Input Capacitor

The input current to the step-down converter is

discontinuous, therefore a capacitor is required to

supply the AC current to the step-down converter

while maintaining the DC input voltage. Ceramic

capacitors

are

recommended

for

best

performance. In the layout, it’s recommended to

put the input capacitor as close as possible to the

VIN pin.

The

capacitance

varies

significantly

over

temperature. Capacitors with X5R and X7R

ceramic dielectrics are recommended because

they are fairly stable over temperature.

The capacitors must also have a ripple current

rating greater than the maximum input ripple

current of the converter. The input ripple current

can be estimated as follows:

OUT

OUT

CIN

OUT

IN

IN

VV

II

(1

)

VV

=×

× −

(15)

where:

OUT

CIN

I

I

2

=

(16)

For simplification, choose the input capacitor

whose RMS current rating is greater than half of

the maximum load current.

The input capacitance value determines the input

voltage ripple of the converter. If there is an input

voltage ripple requirement in the system design,

choose the input capacitor that meets the

specification.The input voltage ripple can be

estimated as follows:

OUT

OUT

OUT

IN

SIN

IN

IN

IV

V

V(1

)

FC

V

V

Δ=

×

× −

×

(17)

where:

OUT

IN

SIN

I

1

V

4F

C

Δ= ×

×

(18)

Output Capacitor

The output capacitor is required to maintain the

DC output voltage. Ceramic or POSCAP

capacitors are recommended. The output voltage

ripple can be estimated as:

OUT

OUT

OUT

ESR

SW

IN

SW

OUT

VV

1

V(1

) (R

)

FL

V

8 F

C

Δ=

× −

×

+

××

×

(19)

In the case of ceramic capacitors, the impedance

at the switching frequency is dominated by the

capacitance. The output voltage ripple is mainly

caused by the capacitance. For simplification, the

output voltage ripple can be estimated by:

OUT

OUT

OUT

2

SOUT

IN

VV

V(1

)

8F

L C

V

Δ=

× −

×× ×

(20)

The output voltage ripple caused by ESR is very

small. Therefore, an external ramp is needed to

stabilize the system. The external ramp can be

generated through resistor R4 and capacitor C4

following equation 4, 7 and 8.

In the case of POSCAP or electrolytic capacitors,

the ESR dominates the impedance at the

switching frequency. The ramp voltage generated

from the ESR is high enough to stabilize the

system.

So

the

external

ramp

is

not

recommended. A minimum ESR value of 12mΩ

is required to ensure stable operation of the

converter. For simplification, the output ripple can

be approximated to:

OUT

OUT

OUT

ESR

SIN

VV

V(1

) R

FL

V

Δ=

× −

×

×

(21)