APA150 datasheet(75/174 Pages) ACTEL

75 / 174 page

ProASICPLUS Flash Family FPGAs

v5.2

1-71

Synchronous FIFO Write

Note: The plot shows the normal operation status.

Figure 1-47 • Synchronous FIFO Write

Table 1-65 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial

TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol txxx

Description

Min.

Max.

Units

Notes

CCYC

Cycle time

7.5

CMH

Clock high phase

3.0

CML

Clock low phase

3.0

DCH

DI hold from WCLKS

↑

0.5

DCS

DI setup to WCLKS

↑

1.0

FCBA

New FULL access from WCLKS

↓

3.01

ECBA

EMPTY

↓ access from WCLKS ↓

3.01

ECBH,

FCBH,

HCBH

Old EMPTY, FULL, EQTH, & GETH valid hold

time from WCLKS

↓

1.0

Empty/full/thresh are invalid from the end of

hold until the new access is complete

HCBA

EQTH or GETH access from WCLKS

↓

4.5

WPCA

New WPE access from WCLKS

↑

3.0

WPE is invalid, while PARGEN is active

WPCH

Old WPE valid from WCLKS

↑

0.5

WRCH, WBCH WRB & WBLKB hold from WCLKS

↑

0.5

WRCS, WBCS

WRB & WBLKB setup to WCLKS

↑

1.0

Notes:

1. At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMH), 3.0 ns.

2. All –F speed grade devices are 20% slower than the standard numbers.

WCLKS

WPE

EMPTY

EQTH, GETH

FULL

(Full Inhibits Write)

WRB, WBLKB

Cycle Start

tWRCH, tWBCH

tECBH, tFCBH

tECBA, tFCBA

tHCBA

tWRCS, tWBCS

tDCS

tWPCA

tCMH

tCML

tCCYC

tWPCH

tDCH

tHCBH

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