PIC12F635EST datasheet(31/234 Pages) MICROCHIP

31 / 234 page

DS41232D-page 29

PIC12F635/PIC16F636/639

2.2.2.4

PIE1 Register

The PIE1 register contains the interrupt enable bits, as

shown in Register 2-4.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0

U-0

R/W-0

EEIE

LVDIE

CRIE

C2IE(1)

C1IE

OSFIE

—TMR1IE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

EEIE: EE Write Complete Interrupt Enable bit

= Enables the EE write complete interrupt

= Disables the EE write complete interrupt

bit 6

LVDIE: Low-Voltage Detect Interrupt Enable bit

= Enables the LVD interrupt

= Disables the LVD interrupt

bit 5

CRIE: Cryptographic Interrupt Enable bit

= Enables the cryptographic interrupt

= Disables the cryptographic interrupt

bit 4

C2IE: Comparator 2 Interrupt Enable bit(1)

= Enables the Comparator 2 interrupt

= Disables the Comparator 2 interrupt

bit 3

C1IE: Comparator 1 Interrupt Enable bit

= Enables the Comparator 1 interrupt

= Disables the Comparator 1 interrupt

bit 2

OSFIE: Oscillator Fail Interrupt Enable bit

= Enables the oscillator fail interrupt

= Disables the oscillator fail interrupt

bit 1

Unimplemented: Read as ‘0’

bit 0

TMR1IE: Timer1 Overflow Interrupt Enable bit

= Enables the Timer1 overflow interrupt

= Disables the Timer1 overflow interrupt

Note 1:

PIC16F636/639 only.

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