ADE7932 datasheet(97/120 Pages) AD

97 / 120 page

Data Sheet

ADE7978/ADE7933/ADE7932

Rev. 0 | Page 97 of 120

Table 58 describes the HCLK, HSIZE, HGAP, HXFER[1:0], and

HSAPOL bits in the HSDC_CFG register. Table 36 lists the time

it takes to execute an HSDC data transfer for all HSDC_CFG

125 μs (8 kHz), which is the update rate of the waveform sample

registers. When the transfer time is less than 125 μs, the HSDC

port transmits data every sampling cycle. When the transfer

time is greater than 125 μs, the HSDC port transmits data only

in the first of two consecutive 8 kHz sampling cycles; that is, the

port transmits registers at an effective rate of 4 kHz.

Table 36. Communication Times for Various HSDC Settings

HXFER[1:0]

HGAP

HSIZE1

HCLK

Communication Time (μs)

N/A

128

77.125

154.25

119.25

238.25

N/A

33.25

66.5

51.625

103.25

N/A

66.625

133.25

1 N/A means not applicable.

HSCLK

HSD

HSA

IAVW (32 BITS)

VAWV (32 BITS)

IBWV (32 BITS)

CFVAR (32 BITS)

Figure 124. HSDC Communication for HGAP = 0, HXFER[1:0] = 00, and HSAPOL = 0; HSIZE Is Irrelevant

HSCLK

HSD

HSA

IAVW (32 BITS)

VAWV (32 BITS)

IBWV (32 BITS)

CVAR (32 BITS)

7 HCLK

CYCLES

7 HCLK

CYCLES

Figure 125. HSDC Communication for HSIZE = 0, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0

HSCLK

HSD

HSA

IAVW (BYTE 3)

IAVW (BYTE 2)

IAVW (BYTE 1)

CVAR (BYTE 0)

7 HCLK

CYCLES

7 HCLK

CYCLES

Figure 126. HSDC Communication for HSIZE = 1, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0

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