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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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EPC2LI20 датащи(PDF) 15 Page - Altera Corporation |
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EPC2LI20 датащи(HTML) 15 Page - Altera Corporation |
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15 / 26 page  IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing Page 15 Configuration Devices for SRAM-Based LUT Devices January 2012 Altera Corporation Figure 4 shows the timing requirements for the JTAG signals. Table 7 lists the timing parameters and values for configuration devices. Figure 4. EPC2 Device JTAG Waveforms Table 7. JTAG Timing Parameters and Values Symbol Parameter Min Max Unit tJCP TCK clock period 100 — ns tJCH TCK clock high time 50 — ns tJCL TCK clock low time 50 — ns tJPSU JTAG port setup time 20 — ns tJPH JTAG port hold time 45 — ns tJPCO JTAG port clock to output — 25 ns tJPZX JTAG port high impedance to valid output — 25 ns tJPXZ JTAG port valid output to high impedance — 25 ns tJSSU Capture register setup time 20 — ns tJSH Capture register hold time 45 — ns tJSCO Update register clock to output — 25 ns tJSZX Update register high impedance to valid output — 25 ns tJSXZ Update register valid output to high impedance — 25 ns TDO TCK tJPZX tJPCO tJPH tJPXZ tJCP tJPSU tJCL tJCH TDI TMS Signal to be Captured Signal to be Driven tJSZX tJSSU tJSH tJSCO tJSXZ |
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