AFE032 datasheet(22/77 Pages) TI1

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From Line-Coupling Circuit

Programmable

Filter

RX_PGA1

RX_PGA2_IN

RX_F_OUT

RX_PGA2_OUT

RX_PGA1_IN

RX_PGA2

To ADC Input of MCU

330 :

RXPGA

)

(

RXPGA

Inside the Device

RRXPGA2IN

RRXPGA1IN

1 k:

AFE032

SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013

www.ti.com

Figure 17 shows the complete Rx signal path, including the optional passive band-pass filter.

(1) For capacitor value C1, f is the desired lower cutoff frequency and RRXPGA1IN is the input resistance of RX_PGA1.

(2) For capacitor value C2, f is the desired lower cutoff frequency and RRXPGA2IN is the input resistance of RX_PGA2.

Figure 17. Complete Rx Signal Path (with Optional Band-Pass Filter)

DAC Block and DSP Path

The AFE032 contains a digital signal processing (DSP) path that receives incoming DAC samples delivered from

an external processor, conditions each sample, and delivers these samples to a 12-bit DAC. The device serial

interface is used to write directly to the DSP path when the DAC pin (pin 7) is driven high. Use the following

sequence to write samples to the DAC:

•

Send a valid XCLK signal to the device (refer to the AFE032 Clock Requirements section for more details on

the XCLK signal).

•

Set CS low.

•

Wait 20 DAC_CLK cycles (refer to the AFE032 Clock Requirements section for more details on the

relationship between the XCLK frequency and DAC_CLK frequency).

•

Set the DAC pin (pin 7) high to configure the device in DAC mode.

•

Write a 12-bit word to DIN. (1) Note that the DAC register is left-justified.

•

Set CS high to indicate that the sample is entered.

Refer to the DAC Mode section for more details on using the device in DAC mode.

The full-scale DAC output swing equals the DAC_NRF voltage level. Table Table 4 shows the ideal dc DAC

output voltage for a given input code.

Table 4. Ideal DAC Output

INPUT CODE (Hex)

IDEAL DAC OUTPUT VOLTAGE (V)

7FF

DAC_NRF bias voltage

001

[(DAC_NRF bias voltage) / (212 – 1)] + (DAC_NRF bias voltage) / 2

000

(DAC_NRF bias voltage) / 2

FFF

[(DAC_NRF bias voltage) / 2] – (DAC_NRF bias voltage) / (212 – 1)

800

(1)

The only exception to the 12-bit DAC sample length is when using a 16-bit envelope. See the SPI Envelope Exception Case section for

more details.

DAC_NRF, PA_NRF, and TX_RX_NRF Blocks

The DAC_NRF, PA_NRF, and TX_RX_NRF blocks create biasing points used internally to the device. Each

reference divides its respective power-supply voltage with a precision resistive voltage divider. PA_NRF provides

a PA_VS / 2 voltage used for the PA; TX_RX_NRF provides an AVDD / 2 voltage used for the Tx PGA, Tx filter,

Rx PGA1, Rx filter, and Rx PGA2; and DAC_NRF provides an AVDD / 4.7 voltage used for the DAC. Each NRF

block has its output brought out to an external pin that can be used for filtering and noise reduction. These

capacitors are optional, but are recommended for best performance.

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