TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I

VOICE-BAND ANALOG INTERFACE CIRCUITS

SLAS017F − MARCH 1988 − REVISED MAY 1995

7

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

D/A low-pass filter, D/A low-pass filter clocking, and D/A conversion timing (continued)

The D/A conversion rate is attained by frequency dividing the 288-kHz switched-capacitor filter clock with TX

Counter B. Unwanted aliasing is prevented because the D/A conversion rate is an integral submultiple of the

switched-capacitor low-pass filter sampling rate, and the two rates are synchronously locked.

asynchronous versus synchronous operation

If the transmit section of the AIC (low-pass filter and DAC) and receive section (bandpass filter and ADC) are

operated asynchronously, the low-pass and bandpass filter clocks are independently generated from the master

clock signal. Also, the D/A and A/D conversion rates are independently determined. If the transmit and receive

sections are operated synchronously, the low-pass filter clock drives both low-pass and bandpass filters. In

synchronous operation, the A/D conversion timing is derived from, and is equal to, the D/A conversion timing

(see description of the WORD/BYTE in the Terminal Functions table.)

D/A converter performance specifications

Fundamental performance specifications for the D/A converter circuitry are presented in the D/A converter

operating characteristics section of the data sheet. The D/A converter has a sample-and-hold that is realized

with a switched-capacitor ladder.

system frequency response correction

The (sin x) / x correction for the D/A converter zero-order sample-and-hold output can be provided by an

on-board second-order (sin x) / x correction filter. This (sin x) / x correction filter can be inserted into or deleted

from the signal path by digital signal processor control. When inserted, the (sin x) / x correction filter follows the

switched-capacitor low-pass filter. When the TB register (see Internal Timing Configuration section) equals 36,

the correction results of Figures 11 and 12 can be obtained.

The (sin x) / x correction can also be accomplished by deleting the on-board second-order correction filter and

performing the (sin x)/ x correction in digital signal processor software. The system frequency response can be

corrected via DSP software to

±0.1-dB accuracy to a band edge of 3000 Hz for all sampling rates. This correction

is accomplished with a first-order digital correction filter, which requires only seven TMS320 (SMJ320)

instruction cycles. With a 200-ns instruction cycle, seven instructions represent an overhead factor of only 1.1%

and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the (sin x)/ x correction section for more details).

serial port

The serial port has four possible modes that are described in detail in the Terminal Functions table. These

modes are briefly described below and in the functional description for WORD/BYTE.

with the DSP.

with the TMS(SMJ)32020, TMS(SMJ)320C25, and the TMS(SMJ)320C30.

with the DSP.

with the TMS(SMJ)32020, TMS(SMJ)320C25, TMS(SMJ)320C30, or two SN74(54)299 serial-to-

parallel shift registers, which can then interface in parallel to the TMS(SMJ)32010, TMS(SMJ)320C15,

and SMJ320E15 to any other digital signal processor or to external FIFO circuitry.