DAC5675

SLAS352C − DECEMBER 2001 − REVISED AUGUST 2004

13

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analog current outputs (continued)

Figure 13(a) shows the typical differential output configuration with two external matched resistor loads. The

nominal resistor load of 25

a 20-mA full-scale output current. The output impedance of the DAC5675 slightly depends on the output voltage

at nodes IOUT1 and IOUT2. Consequently, for optimum dc-integral nonlinearity, the configuration of

Figure 13(b) should be chosen. In this current/voltage (I-V) configuration, terminal IOUT1 is kept at AVDD by

the inverting operational amplifier. The complementary output should be connected to AVDD to provide a

dc-current path for the current sources switched to IOUT1. The amplifier’s maximum output swing and the DACs

edges of the DAC5675 current output, thereby reducing the operational amplifier’s slew-rate requirements. In

this configuration, the op amp should operate at a supply voltage higher than the resistors output reference

voltage AVDD due to its positive and negative output swing around AVDD. Node IOUT1 should be selected if

a single-ended unipolar output is desired.

DAC5675

3.3 V

(AVDD)

25

Ω

25

Ω

3.3 V

(AVDD)

VOUT1

VOUT2

Optional, For

Single-Ended

Output Referred

to AVDD

DAC5675

3.3 V

(AVDD)

+

−

VOUT

200

Ω

Cfb

IOUT1

IOUT2

IOUT1

IOUT2

(a) Unbuffered Differential and

Single-Ended Resistor and Buffered

(b) Buffered Single-Ended Output Configuration

Figure 13. Output Configurations

sleep mode

The DAC5675 features a power-down mode that turns off the output current and reduces the supply current

to approximately 45 mA. The power-down mode is activated by applying a logic level 1 to the SLEEP pin (e.g.,

by connecting the SLEEP pin to the AVDD pin). The SLEEP pin must be connected. Power-up and power-down

activation times depend on the value of the external capacitor at node SLEEP. For a nominal capacitor value

of 0.1-

µF, powerdown takes less than 5 µs and approximately 3 ms to power back up.