Input Clock

Analog

Input

Signal

Sample

N

N + 1

N + 2

N + 3

N + 4

N + 1 4

N + 1 6

N + 1 7

N + 1 5

N − 17

N − 16

N − 15

N − 14

N − 13

N − 3

N − 2

N − 1

N

Data Out

(D0−D11)

17.5 Clock Cycles

Data Invalid

Output Clock

RESET TIMING CHARACTERISTICS

RESET (Pin 35)

SEN Active

Power Supply

ADS5520

A.

It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above

timing matches closely with the specified values.

Figure 1. Timing Diagram

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

Switching Specification

Delay from power-on of AVDD and

10

ms

DRVDD to RESET pulse active

Pulse width of active RESET signal

2

µs

Delay from RESET disable to SEN

2

µs

active

Power-up time

40

ms

Figure 2. Reset Timing Diagram

8

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