APPLICATION INFORMATION

THEORY OF OPERATION

INPUT CONFIGURATION

R

3

R

1a

L

1

L

2

R

1b

C

1a

C

1b

C

A

CP

1

CP

3

VINCM

1V

CP

4

CP

2

INP

INM

All switches OFF Resistance: 10 GW

ADS5520

The ADS5520 is a low-power, 12-Bit, 125 MSPS, CMOS, switched capacitor, pipeline ADC that operates from a

single 3.3-V supply. The conversion process is initiated by a falling edge of the external input clock. Once the

signal is captured by the input S&H, the input sample is sequentially converted by a series of small resolution

stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges

are used to propagate the sample through the pipeline every half clock cycle. This process results in a data

latency of 17.5 clock cycles, after which the output data is available as a 12-bit parallel word, coded in either

straight offset binary or binary 2's complement format.

The analog input for the ADS5520 consists of a differential sample-and-hold architecture implemented using the

switched capacitor technique shown in Figure 39.

A.

All Switches are ON in sampling phase which is approximately one half of a clock period.

Figure 39. Analog Input Stage

22

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