AD9517-0ASLASHPCBZ datasheet(46/80 Pages) AD

46 / 80 page

AD9517-0

Data Sheet

Rev. E | Page 46 of 80

Table 44. Divider 2 and Divider 3 Duty Cycle; VCO Divider

Not Used; Duty Cycle Correction On (DCCOFF = 0)

Input

Clock

Duty

Cycle

DX.1

DX.2

Output Duty Cycle

NX.1 + MX.1 + 2

NX.2 + MX.2 + 2

50%

Even

(NX.1 = MX.1)

50%

X% (High)

Even

(NX.1 = MX.1)

50%

Odd

(MX.1 = NX.1 + 1)

50%

Odd

(MX.1 = NX.1 + 1)

(NX.1 + 1 + X%)/

(2NX.1 + 3)

50%

Even

(NX.1 = MX.1)

Even

(NX.2 = MX.2)

50%

Even

(NX.1 = MX.1)

Even

(NX.2 = MX.2)

50%

Odd

(MX.1 = NX.1 + 1)

Even

(NX.2 = MX.2)

50%

Odd

(MX.1 = NX.1 + 1)

Even

(NX.2 = MX.2)

50%

Odd

(MX.1 = NX.1 + 1)

Odd

(MX.2 = NX.2 + 1)

50%

Odd

(MX.1 = NX.1 + 1)

Odd

(MX.2 = NX.2 + 1)

(2NX.1NX.2 + 3NX.1 +

3NX.2 + 4 + X%)/

((2NX.1 + 3)(2NX.2 + 3))

Phase Offset or Coarse Time Delay (Divider 2 and Divider 3)

Divider 2 and Divider 3 can be set to have a phase offset or

delay. The phase offset is set by a combination of the bits in the

phase offset and start high registers (see Table 45).

Table 45. Setting Phase Offset and Division for Divider 2 and

Divider 3

Divider

Start

High (SH)

Phase

Offset (PO)

Low

Cycles M

High

Cycles N

2.1

0x19C[0]

0x19A[3:0]

0x199[7:4]

0x199[3:0]

2.2

0x19C[1]

0x19A[7:4]

0x19B[7:4]

0x19B[3:0]

3.1

0x1A1[0]

0x19F[3:0]

0x19E[7:4]

0x19E[3:0]

3.2

0x1A1[1]

0x19F[7:4]

0x1A0[7:4]

0x1A0[3:0]

Let

Δt = delay (in seconds).

Φx.y = 16 × SH[0] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] +

1 × PO[0].

TX.1 = period of the clock signal at the input to DX.1 (in seconds).

TX.2 = period of the clock signal at the input to DX.2 (in seconds).

Case 1

When Φx.1 ≤ 15 and Φx.2 ≤ 15:

Δt = Φx.1 × TX.1 + ΦX.2 × Tx.2

Case 2

When Φx.1 ≤ 15 and Φx.2 ≥ 16:

Δt = ΦX.1 × TX.1 + (ΦX.2 − 16 + MX.2 + 1) × TX.2

Case 3

When ΦX.1 ≥ 16 and ΦX.2 ≤ 15:

Δt = (ΦX.1 − 16 + MX.1 + 1) × TX.1 + ΦX.2 × TX.2

Case 4

When ΦX.1 ≥ 16 and ΦX.2 ≥ 16:

Δt =

(ΦX.1 − 16 + MX.1 + 1) × TX.1 + (ΦX.2 − 16 + MX.2 + 1) × TX.2

Fine Delay Adjust (Divider 2 and Divider 3)

Each AD9517 LVDS/CMOS output (OUT4 to OUT7) includes

an analog delay element that can be programmed to give

variable time delays (Δt) in the clock signal at that output.

DIVIDER

X.2

DIVIDER

X.1

ΔT

OUTM

BYPASS

FINE DELAY

ADJUST

CMOS

LVDS

CMOS

ΔT

OUTN

BYPASS

FINE DELAY

ADJUST

CMOS

LVDS

CMOS

OUTPUT

DRIVERS

CLK

VCO

DIVIDER

Figure 56. Fine Delay (OUT4 to OUT7)

The amount of delay applied to the clock signal is determined

by programming four registers per output (see Table 46).

Table 46. Setting Analog Fine Delays

OUTPUT

(LVDS/CMOS)

Ramp

Capacitors

Ramp

Current

Delay

Fraction

Delay

Bypass

OUT4

0x0A1[5:3]

0x0A1[2:0]

0x0A2[5:0]

0x0A0[0]

OUT5

0x0A4[5:3]

0x0A4[2:0]

0x0A5[5:0]

0x0A3[0]

OUT6

0x0A7[5:3]

0x0A7[2:0]

0x0A8[5:0]

0x0A6[0]

OUT7

0x0AA[5:3]

0x0AA[2:0]

0x0AB[5:0]

0x0A9[0]

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