AD7274 datasheet(9/29 Pages) AD

9 / 29 page

AD7273/AD7274

Rev. 0 | Page 8 of 28

TIMING EXAMPLES

For the AD7274, if CS is brought high during the 14

th SCLK

rising edge after the two leading zeros and 12 bits of the

conversion are provided, the part can achieve the fastest

throughput rate, 3 MSPS. If CS is brought high during the 16

SCLK rising edge after the two leading zeros, 12 bits of the

conversion, and two trailing zeros are provided, a throughput

rate of 2.97 MSPS is achievable. This is illustrated in the

following two timing examples.

Timing Example 1

In Figure 6, using a 14 SCLK cycle, fSCLK = 48 MHz, and

the throughput is 3 MSPS. This produces a cycle time of

t2 + 12.5(1/fSCLK) + tACQ = 333 ns, where t2 = 6 ns min and

tACQ = 67 ns. This satisfies the requirement of 60 ns for tACQ.

Figure 6 also shows that tACQ comprises 0.5(1/fSCLK) + t9 + tQUIET,

where t9 = 4.2 ns max. This allows a value of 52.8 ns for tQUIET,

satisfying the minimum requirement of 4 ns.

Timing Example 2

The example in Figure 7 uses a 16 SCLK cycle, fSCLK = 48 MHz,

and the throughput is 2.97 MSPS. This produces a cycle time

of t2 + 12.5(1/fSCLK) + tACQ = 336 ns, where t2 = 6 ns min and

tACQ = 70 ns. Figure 7 shows that tACQ comprises 2.5(1/fSCLK) +

t8 + tQUIET, where t8 = 14 ns max. This satisfies the minimum

requirement of 4 ns for tQUIET.

SCLK

SDATA

THREE-STATE

THREE-

STATE TWO LEADING

ZEROS

TWO TRAILING

ZEROS

tCONVERT

ZERO

DB11

DB10

DB9

DB1

DB0

ZERO

tQUIET

1/THROUGHPUT

Figure 5. AD7274 Serial Interface Timing 16 SCLK Cycle

SCLK

SDATA

THREE-STATE

THREE-

STATE

TWO LEADING

ZEROS

tCONVERT

ZERO

DB11

DB10

DB9

DB1

DB0

tQUIET

1/THROUGHPUT

Figure 6.AD7274 Serial Interface Timing 14 SCLK Cycle

SCLK

tCONVERT

tQUIET

1/THROUGHPUT

12.5(1/fSCLK)

tACQUISITION

Figure 7. Serial Interface Timing 16 SCLK Cycle

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