AD558

REV. A

–7–

OUTPUT

AMP

16

15

14

13

AGND

–V

0.5mA

b. 0 V to 10 V Output Range

Figure 11. Offset Connection Diagrams

INTERFACING THE AD558 TO MICROPROCESSOR

DATA BUSES

The AD558 is configured to act like a “write only” location in

memory that may be made to coincide with a read only memory

location or with a RAM location. The latter case allows data

previously written into the DAC to be read back later via the

RAM. Address decoding is partially complete for either ROM

or RAM. Figure 12 shows interfaces for three popular micropro-

cessor systems.

ADDRESS BUS

DATA BUS

6800

VMA

R/W

AD558

DB0–DB7

16

8

8

CE

CS

ADDRESS

DECODER

16

R/W

→ CE

GATED DECODED ADDRESS

→ CS

a. 6800/AD558 Interface

ADDRESS BUS

DATA BUS

8080A

AD558

DB0–DB7

16

8

8

CE

CS

ADDRESS SELECT

PULSE LOGIC

16

MEMW

MEMW

→ CE

DECODED ADDRESS SELECT PULSE

→ CS

b. 8080A/AD558 Interface

ADDRESS BUS

DATA BUS

1802

AD558

DB0–DB7

8

8

8

CE

CS

ADDRESS

LATCH

&

DECODE

8

MWR

CDP 1802: MWR

→ CE

DECODED ADDRESS SELECT PULSE

→ CS

TPA

MA 0 – 7

c. 1802/AD558 Interface

Figure 12. Interfacing the AD558 to Microprocessors

CC

+5 V to +15 V unless otherwise noted)

0

LSB

1.75

1.50

1.25

1.00

0.75

0.50

0.25

–0.25

–0.50

–0.75

–1.00

–55

–25

0

+25

+50

+75

+100

+125

oC

FULL

SCALE

ERROR

ALL AD558

AD558S, T

1LSB = 0.39% OF FULL SCALE

Figure 13. Full-Scale Accuracy vs. Temperature

Performance of AD558

0

LSB

1/2

1/4

–55

–25

0

+25

+50

+75

+100

+125

oC

ZERO

ERROR

ALL AD558

AD558S, T

1LSB = 0.39% OF FULL SCALE

–1/4

–1/2

Figure 14. Zero Drift vs. Temperature Performance

of AD558