APL3206 datasheet(13/19 Pages) ANPEC

13 / 19 page

Rev. A.4 - Jan., 2010

APL3206/A/B

www.anpec.com.tw

Application Information

BAT Selection

Connect the VBAT pin to the positive terminal of battery

through a resistor R

BAT for battery OVP function. The RBAT

limits the current flowing from VBAT to battery in case of

VBAT pin is shortened to ACIN pin under a failure mode.

The recommended value of R

BAT is 200kΩ. In the worse

case of an IC failure, the current flowing from the VBAT

pin to the battery is:

(30V-3V) / 200k

Ω =135µA

where the 30V is the maximum ACIN voltage and the 3V

is the minimum battery voltage. The current is so small

and can be absorbed by the charger system.

Capacitor Selection

The input capacitor is for decoupling and prevents the

input voltage from overshooting to dangerous levels. In

the AC adapter hot plug-in applications or load current

step-down transient, the input voltage has a transient

spike due to the parasitic inductance of the input cable. A

25V, X5R, dielectric ceramic capacitor with a value be-

tween 1

µF and 4.7µF placed close to the ACIN pin is

recommended.

The output capacitor of CHRIN is for CHRIN voltage

decoupling. And also can be as the input capacitor of the

charging circuit. At least, a 1

µF, 10V, X5R capacitor is

recommended.

Layout Consideration

In some failure modes, a high voltage may be applied to

the device. Make sure the clearance constraint of the PCB

layout must satisfy the design rule for high voltage. The

exposed pad of the TDFN2x2-8 performs the function of

channeling heat away. It is recommended that connect

the exposed pad to a large copper ground plane on the

backside of the circuit board through several thermal vias

to improve heat dissipation. The input and output capaci-

tors should be placed close to the IC. The high current

traces like input trace and output trace must be wide and

short.

Thermal Considerations

The maximum power dissipation depends on the ther-

mal resistance of IC package, PCB layout, the rate of

surroundings airflow and temperature difference between

junction to ambient. The maximum power dissipation can

be calculated by the following formula:

D(MAX) = (TJ(MAX)-TA) / θJA

Where T

J(MAX) is

the maximum operation junction

temperature, T

A is the ambient temperature and the θJA is

the junction to ambient thermal resistance. For recom-

mended operating conditions specification of APL3206/

A, where T

J(MAX) is 125

oC and T

A is the operated ambient

temperature. The junction to ambient thermal resistance

JA for TDFN2x2-8 package is 165

oC/W and TSOT-23-6A

package is 220oC/W on the standard JEDEC 51-3 single-

layer thermal test board. The maximum power dissipa-

tion at T

A = 25

oC can be calculated by following formula :

D(MAX) = (125

oC-25oC) / (165oC/W) = 0.606W

for TDFN2x2-8 packages

D(MAX) = (125

oC-25oC) / (220oC/W)= 0.455W

for TSOT-23-6A packages

The maximum power dissipation depends on operating

ambient temperature for fixed T

J(MAX) and thermal resis-

tance

JA. For APL3206/A packages, the Figure 4 of derat-

ing curves allows the designer to see the effect of rising

ambient temperature on the maximum power allowed.

Figure 4. Derating Curves for APL3206/A Packages

Ambient Temperature ( oC)

TSOT-23-6A

TDFN2x2-8

Signal Layer PCB

100

125

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

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