AD7276 datasheet(21/28 Pages) AD

21 / 28 page

AD7273/AD7274

Rev. 0 | Page 20 of 28

POWER VS. THROUGHPUT RATE

Figure 34 shows the power consumption of the device in

normal mode, in which the part is never powered down. By

using the power-down mode of the AD7273/AD7274 when not

performing a conversion, the average power consumption of the

ADC decreases as the throughput rate decreases.

Figure 35 shows that as the throughput rate is reduced, the

device remains in its power-down state longer and the average

power consumption over time drops accordingly. For example,

if the AD7273/AD7274 are operated in continuous sampling

mode with a throughput rate of 200 kSPS and a SCLK of 48 MHz

(VDD = 3 V) and the devices are placed into power-down mode

between conversions, the power consumption is calculated as

follows. The power dissipation during normal operation is

11.6 mW (VDD = 3 V). If the power-up time is one dummy

cycle, that is, 333 ns, and the remaining conversion time is

290 ns, the AD7273/AD7274 can be said to dissipate 11.6 mW

for 623 ns during each conversion cycle. If the throughput rate

is 200 kSPS, the cycle time is 5 μs and the average power dissipated

during each cycle is 623/5,000 × 9.6 mW = 1.42 mW. Figure 35

shows the power vs. throughput rate when using the partial

power-down mode between conversions at 3 V. The power-

down mode is intended for use with throughput rates of less

than 600 kSPS, because at higher sampling rates there is no

power saving achieved by using the power-down mode.

THROUGHPUT (kSPS)

3.40

3.80

4.20

4.60

5.00

5.40

5.80

6.20

6.60

7.00

200

400

600

800

1000

1200

1400

1600

1800

2000

VDD = 3V

48MHz SCLK

VARIABLE SCLK

Figure 34. Power vs. Throughput, Normal Mode

THROUGHPUT (kSPS)

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

3.6

4.0

4.4

4.8

5.2

5.6

6.0

6.4

6.8

7.2

200

400

600

800

1000

VDD = 3V

Figure 35. Power vs. Throughput, Partial Power-Down Mode

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