AD7873

Data Sheet

Rev. F | Page 20 of 28

Table 8. Power Management Options

PD1

PD0

PENIRQ

Description

0

0

Enabled

This configuration results in immediate power-down of the on-chip reference as soon as PD1 is set to 0. The ADC

powers down only between conversions. When PD0 is set to 0, the conversion is performed first and the ADC

powers down upon completion of that conversion (or upon the rising edge of CS, if it occurs first). At the start of

the next conversion, the ADC instantly powers up to full power. This means if the device is being used in the

differential mode, or an external reference is used, there is no need for additional delays to ensure full operation

and the very first conversion is valid. The Y– switch is on while in power-down. When the device is performing

differential table conversions, the reference and reference buffer do not attempt to power up with Bit PD1 and

Bit PD0 programmed in this way.

0

1

Enabled

This configuration results in switching the reference off immediately and the ADC on permanently. When the

device is performing differential tablet conversions, the reference and reference buffer do not attempt to power

up with Bit PD1 and Bit PD0 programmed in this way.

1

0

Enabled

This configuration results in switching the reference on and powering the ADC down between conversions. The

ADC powers down only between conversions. When PD0 is set to 0, the conversion is performed first, and the

ADC powers down upon completion of the conversion (or upon the rising edge of CS if it occurs first). At the start

of the next conversion, the ADC instantly powers up to full power. There is no need for additional delays to ensure

full operation as the reference remains permanently powered up.

1

1

Disabled

This configuration results in always keeping the device powered up. The reference and the ADC are on.

POWER VS. THROUGHPUT RATE

By using the power-down options on the AD7873 when not

converting, the average power consumption of the device

decreases at lower throughput rates. Figure 35 shows how, as

the throughput rate is reduced while maintaining the DCLK

frequency at 2 MHz, the device remains in its power-down state

longer and the average current consumption over time drops

accordingly.

Figure 35. Supply Current vs. Throughput (µA)

For example, if the AD7873 is operated in a 24-DCLK continuous

sampling mode, with a throughput rate of 10 kSPS and a DCLK

of 2 MHz, and the device is placed in the power-down mode

between conversions, (PD0, PD1 = 0, 0), that is, the ADC shuts

down between conversions but the reference remains powered

down permanently, then the current consumption is calculated

as follows. The current consumption during normal operation

external reference is used, the power-up time of the ADC is

instantaneous, so when the part is converting, it consumes

210 µA. In this mode of operation, the part powers up on the

fourth falling edge of DCLK after the start bit is recognized. It

goes back into power-down at the end of conversion on the

20th falling edge of DCLK, meaning that the part consumes

210 µA for 16 DCLK cycles only, 8 µs during each conversion

cycle. If the throughput rate is 10 kSPS, the cycle time is 100 µs

and the average power dissipated during each cycle is

(8/100) × (210 µA) = 16.8 µA.

1

100

10

1000

0

120

THROUGHPUT (kSPS)

40

60

0

20

80

100