AD7729

–9–

REV. 0

FUNCTIONAL DESCRIPTION

BASEBAND CODEC

Receive Section

The receive section consists of I and Q receive channels, each

comprising of a simple switched-capacitor filter followed by a

15-bit sigma-delta ADC. On-board digital filters, which form

part of the sigma-delta ADCs, also perform critical system-level

filtering. Their amplitude and phase response characteristics

provide excellent adjacent channel rejection. The receive sec-

tion is also provided with a low power sleep mode to place the

receive section on standby between receive bursts, drawing only

minimal current.

Switched Capacitor Input

The receive section analog front-end is sampled at 13 MHz by a

switched-capacitor filter. The filter has a zero at 6.5 MHz as

shown in Figure 8a. The receive channel also contains a digital

low-pass filter (further details are contained in the following

section) which operates at a clock frequency of 6.5 MHz. Due

to the sampling nature of the digital filter, the passband is re-

peated about the operating clock frequency and at multiples of

the clock frequency (Figure 8b). Because the first null of the

switched-capacitor filter coincides with the first image of the

digital filter, this image is attenuated by an additional 30 dBs

(Figure 8c), further simplifying the external antialiasing require-

ments (see Figures 9 and 10).

FRONT-END

ANALOG FILTER

TRANSFER

FUNCTION

0 dBs

6.5

13

19.5

MHz

a) Switched-Cap Filter Frequency Response

MHz

6.5

13

19.5

DIGITAL FILTER

TRANSFER

FUNCTION

0 dBs

b) Digital Filter Frequency Response

MHz

6.5

13

19.5

SYSTEM FILTER

TRANSFER

FUNCTION

0 dBs

c) Overall System Response of the Receive

Channel

Figure 8.

The circuitry of Figure 9 implements first-order low-pass filters

with a 3 dB point at 338 kHz; these are the only filters that

must be implemented external to the baseband section to pre-

vent aliasing of the sampled signal.

VOLTAGE

REFERENCE

0.1 F

0.1 F

REFCAP

REFOUT

TO INPUT BIAS

CIRCUITRY

100pF

100pF

4.7k

4.7k

4.7k

4.7k

100pF

100pF

I CHANNEL

Q CHANNEL

AD7729

IRxP

IRxN

QRxP

QRxN

IRx

QRx

Figure 9. Example Circuit for Differential Input

Figure 10 shows the recommended single-ended analog input

circuit.

VOLTAGE

REFERENCE

0.1 F

0.1 F

REFCAP

REFOUT

100pF

4.7k

4.7k

100pF

I CHANNEL

Q CHANNEL

AD7729

IRxP

IRxN

QRxP

QRxN

IRx

QRx

HIGH SPEED

BUFFER

Figure 10. Example Circuit for Single-Ended Input