AD977/AD977A

–11–

REV. D

EXTERNAL DISCONTINUOUS CLOCK DATA READ

DURING CONVERSION WITH SYNC OUTPUT

GENERATED

Figure 7 illustrates the method by which data from conversion

“n-1” can be read during conversion “n” while using a discon-

tinuous external clock, with the generation of a SYNC output.

What permits the generation of a SYNC output is a transition of

DATACLK while either

CS is High or while both CS and R/C

are low. In Figure 7 a conversion is initiated by taking R/

C low

with

CS tied low. While this condition exists a transition of

DATACLK, clock pulse #0, will enable the generation of a

SYNC pulse. Less then 83 ns after R/

C is taken low the BUSY

output will go low to indicate that the conversion process has

began. Figure 7 shows R/

C then going high and after a delay of

request the SYNC output. The SYNC output will appear

approximately 40 ns after this rising edge and will be valid on

the falling edge of clock pulse #1 and the rising edge of clock

pulse #2. The MSB will be valid approximately 40 ns after the

rising edge of clock pulse #2 and can be latched off either the

falling edge of clock pulse #2 or the rising edge of clock pulse

#3. The LSB will be valid on the falling edge of clock pulse #17

and the rising edge of clock pulse #18. Approximately 40 ns

after the rising edge of clock pulse #18, the DATA output

pin will reflect the state of the TAG input pin during the

rising edge of clock pulse #2.

BUSY

R/C

EXT

DATACLK

BIT 15

(MSB)

BIT 14

12

DATA

SYNC

0

3

17

18

BIT 0

(LSB)

TAG 0

TAG 1

TAG 0

TAG 1

TAG 2

TAG 16

TAG 17

TAG 18

TAG 19

TAG

TAG 2

4

Figure 6. Conversion and Read Timing Using An External Discontinuous Data Clock (EXT/

INT Set to Logic High, CS Set

to Logic Low)

BUSY

R/C

EXT

DATACLK

BIT 15

(MSB)

BIT 14

12

DATA

SYNC

0

318

BIT 0

(LSB)

TAG 0

t

20

Figure 7. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion Using External

Discontinuous Data Clock (EXT/

INT Set to Logic High, CS Set to Logic Low)