AD1835AASZ datasheet(13/24 Pages) AD

13 / 24 page

REV. A

AD1835A

–13–

The format is similar to the Motorola SPI format except the

input data-word is 16 bits wide. The maximum serial bit clock

frequency is 12.5 MHz and may be completely asynchronous

to the sample rate of the ADCs and DACs. Figure 3 shows the

format of the SPI signal.

Serial Data Ports—Data Format

The ADC serial data output mode defaults to the popular I

format, where the data is delayed by 1 BCLK interval from the

edge of the LRCLK. By changing Bits 6 to 8 in ADC Control

(RJ), left-justified DSP (DSP), or left-justified (LJ). In the

RJ mode, it is necessary to set Bits 4 and 5 to define the width

of the data-word.

The DAC serial data input mode defaults to I

2S. By changing

Bits 5, 6, and 7 in DAC Control Register 1, the mode can be

changed to RJ, DSP, LJ, Packed Mode 1, or Packed Mode 2.

The word width defaults to 24 bits but can be changed by

reprogramming Bits 3 and 4 in DAC Control Register 1.

Packed Modes

The AD1835A has a packed mode that allows a DSP or other

controller to write to all DACs and read all ADCs using one input

data pin and one output data pin. Packed Mode 256 refers to

the number of BCLKs in each frame. The LRCLK is low while

data from a left channel DAC or ADC is on the data pin and

high while data from a right channel DAC or ADC is on the

data pin. DAC data is applied on the DSDATA1 pin and ADC

data is available on the ASDATA pin. Figures 7 to 12 show the

timing for the packed mode. Packed mode is available for 48 kHz

and 96 kHz.

Auxiliary (TDM) Mode

A special auxiliary mode is provided to allow three external stereo

ADCs to be interfaced to the AD1835A to provide 8-in/8-out

operation. In addition, this mode supports glueless interface to

a single SHARC DSP serial port, allowing a SHARC DSP to

access all eight channels of analog I/O. In this special mode,

many pins are redefined; see Table IV for a list of redefined pins.

The auxiliary and TDM interfaces are independently configurable

to operate as masters or slaves. When the auxiliary interface is

set as a master, by programming the auxiliary mode bit in

ADC Control Register 2, the AUXLRCLK and AUXBCLK

are generated by the AD1835A. When the auxiliary interface is

set as a slave, the AUXLRCLK and AUXBCLK need to be

generated by an external ADC as shown in Figure 15.

The TDM interface can be set to operate as a master or slave by

connecting the

M/S pin to DGND or ODVDD, respectively. In

master mode, the FSTDM and BCLK signals are outputs and

are generated by the AD1835A. In slave mode, the FSTDM

and BCLK are inputs and should be generated by the SHARC.

Both 48 kHz and 96 kHz operations are available (based on a

12.288 MHz or 24.576 MHz MCLK) in this mode.

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LEFT CHANNEL

RIGHT CHANNEL

LEFT CHANNEL

RIGHT CHANNEL

LEFT CHANNEL

RIGHT CHANNEL

MSB

LSB

LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL

I2S MODE – 16 BITS TO 24 BITS PER CHANNEL

RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL

DSP MODE – 16 BITS TO 24 BITS PER CHANNEL

1/fS

NOTES

1. DSP MODE DOES NOT IDENTIFY CHANNEL.

2. LRCLK NORMALLY OPERATES AT

fS EXCEPT FOR DSP MODE, WHICH IS 2

fS.

3. BCLK FREQUENCY IS NORMALLY 64

LRCLK BUT MAY BE OPERATED IN BURST MODE.

Figure 4. Stereo Serial Modes

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