ADM1184

Rev. 0 | Page 9 of 12

THEORY OF OPERATION

The ADM1184 is an integrated, 4-channel voltage-monitoring

device. A 2.7 V to 5.5 V power supply is required on the VCC pin

to power the device.

2.5V

3.3V

1.8V

1.2V

OUT1

VIN1

OUT2

VIN2

OUT3

VIN3

VIN4

GND

PWRGD

POWER

GOOD

VCC

ADM1184

ENABLE

SIGNALS

Figure 16. Typical Applications Circuit

INPUT CONFIGURATION

Four precision comparators monitor four voltage rails.

Each comparator has a 0.6 V reference with a worst-case

accuracy of 0.8%. Resistor networks external to the VIN1,

VIN2, VIN3, and VIN4 pins set the trip points for the

monitored supply rails.

Typically, the threshold voltage at each of the four adjustable

inputs (that is, VIN1, VIN2, VIN3, and VIN4) is 0.6 V. To

monitor a voltage greater than 0.6 V, connect a resistor divider

network to the circuit as depicted in Figure 17.

VIN1

1.2kΩ

4.6kΩ

0.6V

TO LOGIC

CORE

ADM1184

3.3V

2.9V

0V

V

t

2.9V SUPPLY

GIVES 0.6V

AT VIN1 PIN

Figure 17. Setting the Undervoltage Threshold

In this example, the VIN1 pin monitors a 3.3 V supply. An

external resistor divider scales this voltage down for monitoring

at the VIN1 pin. The resistor ratio is chosen so that the VIN1

voltage is 0.6 V when the main voltage rises to the preferred level

at startup (a voltage below the nominal 3.3 V level). R1 is 4.6 kΩ

and R2 is 1.2 kΩ; therefore, a voltage level of 2.9 V corresponds

to 0.6 V on the noninverting input of the first comparator (see

Figure 17).

OUTPUT CONFIGURATION

The ADM1184 has four open-drain, active high outputs. Of

these outputs, OUT1 to OUT3 can be used to enable power

supplies, and PWRGD is a common power-good output.

Output OUT1 to Output OUT3 are dependent on their associated

input (that is, VIN1, VIN2, or VIN3). Before the voltage on a

VINx input reaches 0.6 V, the corresponding output is switched

to ground if there is 1 V on the VCC pin of the ADM1184. When

VINx detects 0.6 V, OUTx is asserted after a 30 μs (typical) delay.

When all four monitored supplies exceed 0.6 V, a system power-

good signal (PWRGD) is asserted. There is an internal 190 ms

(typical) delay associated with the assertion of the PWRGD

output. After PWRGD is asserted, if any of the four monitored

supplies drops below its programmed threshold, the corresponding

OUTx output and the PWRGD output are deasserted. If only

the supply monitored by VIN4 drops below its programmed

threshold, just the PWRGD output is deasserted.

The ADM1184 functional truth table is shown in Table 5. Note that

the functional operation described in Table 5 applies to the

operation both before and after the assertion of PWRGD.

Table 5. Functional Truth Table

VIN1

VIN2

VIN3

VIN4

OUT1

OUT2

OUT3

PWRGD

0

0

0

Low

Low

Low

Low

0

0

0

Low

Low

Low

Low

0

0

1

0

Low

Low

High

Low

0

0

1

1

Low

Low

High

Low

0

1

0

0

Low

High

Low

Low

0

1

0

1

Low

High

Low

Low

0

1

1

0

Low

High

High

Low

0

1

1

1

Low

High

High

Low

1

0

0

0

High

Low

Low

Low

1

0

0

1

High

Low

Low

Low

1

0

1

0

High

Low

High

Low

1

0

1

1

High

Low

High

Low

1

1

0

0

High

High

Low

Low

1

1

0

1

High

High

Low

Low

1

1

1

0

High

High

High

Low

1

1

1

1

High

High

High

High

Figure 18 and Figure 19 show waveforms that illustrate the

behavior of the ADM1184.