PCF8537 datasheet(68/82 Pages) NXP

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PCF8537

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Product data sheet

Rev. 1 — 31 May 2012

68 of 82

NXP Semiconductors

PCF8537

Industrial LCD driver for multiplex rates up to 1:8

[1]

Internal calibration made with OTP so that the maximum variation is

15 % over whole temperature and voltage range. The typical f

clk

frequency generates a typical frame frequency of 200 Hz when the default frequency division factor is used.

[2]

The typical value is defined at VDD1 =VDD2 = 5.0 V and 30 C.

[3]

All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an

input voltage swing of VSS to VDD.

[4]

tVD;DAT = minimum time for valid SDA output following SCL LOW.

[5]

tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW.

Table 38.

Timing characteristics: I2C-bus

VDD1 = 1.8 V to 5.5 V; VDD2 = 2.5 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fSCL

SCL clock frequency

400

kHz

tBUF

bus free time between a

STOP and START condition

1.3

s

tHD;STA

hold time (repeated) START

condition

0.6

s

tSU;STA

set-up time for a repeated

START condition

0.6

s

tVD;DAT

data valid time

[4]

--0.9

s

tVD;ACK

data valid acknowledge time

[5]

--0.9

s

tLOW

LOW period of the SCL clock

1.3

s

tHIGH

HIGH period of the SCL clock

0.6

s

fall time

of both SDA and SCL signals

0.3

s

rise time

of both SDA and SCL signals

0.3

s

capacitive load for each bus

line

400

tSU;DAT

data set-up time

100

tHD;DAT

data hold time

tSU;STO

set-up time for STOP

condition

0.6

s

tw(spike)

spike pulse width

Fig 60. I2C-bus timing waveforms

SCL

SDA

tHD;STA

tSU;DAT

tHD;DAT

tBUF

tSU;STA

tLOW

tHIGH

tVD;ACK

013aaa417

tSU;STO

protocol

START

condition

(S)

bit 7

MSB

(A7)

bit 6

(A6)

bit 0

(R/W)

acknowledge

(A)

STOP

condition

(P)

1/fSCL

tVD;DAT

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