74LVC07A

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© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 5 — 27 October 2011

2 of 14

NXP Semiconductors

74LVC07A

Hex buffer with open-drain outputs

4.

Functional diagram

5.

Pinning information

5.1 Pinning

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

Fig 3.

Logic diagram for one gate

mna535

2

11A

1Y

4

32A

2Y

6

53A

3Y

8

94A

4Y

10

11

5A

5Y

12

13

6A

6Y

mna534

1A

2A

3A

4A

5A

6A

1Y

2Y

3Y

4Y

5Y

6Y

2

1

1

4

3

6

5

8

9

10

11

12

13

1

1

1

1

1

mna533

GND

A

Y

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 4.

Pin configuration for SO14 and TSSOP14

Fig 5.

Pin configuration for DHVQFN14

74LVC07A

1A

1Y

6A

2A

6Y

2Y

5A

3A

5Y

3Y

4A

GND

4Y

001aad066

1

2

3

4

5

6

7

8

10

9

12

11

14

13

001aad067

74LVC07A

Transparent top view

3Y

4A

3A

5Y

2Y

5A

2A

6Y

1Y

6A

6

9

5

10

4

11

3

12

2

13

terminal 1

index area