AD9961-EBZ datasheet(58/61 Pages) AD

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AD9961/AD9963

Data Sheet

Rev. A | Page 58 of 60

EXAMPLE START-UP SEQUENCES

CONFIGURING THE DLL

The AD9963 DLL is shown in Figure 65, the clock distribution

diagram. The register writes in Table 31 configures the DLL

to drive the DACs with a multiplication in frequency of 10

and a division of 3 from the main CLKP/CLKN input. From

the default register settings at reset, this would take a 20 MHz

CLKP/CLKN clock, multiply it up to 200 MHz, then divide

the clock down by 3 to produce 66.67 MHz. The write to

the DLL. By default, the Rx and Tx data buses operate in SDR

mode. Each DAC is clocked at 66.67 MHz and the TxCLK pin

outputs 133.33 MHz.

Table 31.

(hex)

Data

(hex)

Comments

0x60

0x80

% enable DLL

0x71

0x53

% set DAC clock to DLL/enable DLL

reference/N = 3

0x72

0x09

% M = 9, effective multiplication is M +

1 = 10

Delay 100 pS

0x75

0x08

% hold DLL reset high

0xDelay 100 pS

0x75

0x00

% hold DLL reset low

0x72

Read

% check Bit 7 to verify the DLL has

locked

CONFIGURING THE CLOCK DOUBLERS (DDLL)

The AD9963 includes two clock doublers. The Rx clock

doubler, if enabled, doubles the frequency of the CLKP/CLKN

signal on its way into the circuit that generates ADCCLK

(Figure 65). The Tx clock doubler doubles the DACCLK signal

and can be selected to be included in the TxCLK generator

circuit (Figure 52). Use of both clock doublers is recommended

when the ADCs and DACs are operated above 15 MHz.

When operating below 75 MHz, bypass the duty cycle stabilizer

in the ADCCLK generator circuit and take care to ensure a duty

cycle 45% to 55% of the CLKP/CLKN clock input. The series

of writes in Table 32 configures the Rx clock doubler to clock

the ADCs from reset. These writes are for an ADC clock of

< 75 MHz.

This same sequence could be used for setting up a clock

>75 MHz by removing the write to Register 0x66.

Table 32.

(hex)

Data

(hex)

Comments

0x3C

0x00

% the recommended tap delay is 0

0x39

0x02

% configure RxCLK as DDLL

0x66

0x04

% bypass duty cycle correction (for

CLKP/CLKN < 75 MHz)

0x3B

0x55

% the recommended offset is 1

(changing Bit 3 from default)

Delay 100 pS

0x39

0x82

% reset Rx DDLL

Delay 100 pS

0x39

0x02

% pull Rx DDLL out of reset

0x63

0x08

% set drive strength to 3 for the RxClk

SENSING TEMPERATURE WITH THE AUXADC

This sequence of register writes and reads configures the

AUXADC to sense temperature.

(hex)

Data

(hex)

Comments

0x77

0x03

Channel temperature sensor

0x7A

0x80

Aux ADC enable

0x7B

0x80

Temperature sensor enable

0x77

0x83

Choose channel to sample with AUX ADC

Read

0x78

MSB 7:0 = AUXADC[11:4]

Read

0x79

LSB bit 7:4 = AUXADC[3:0]

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