TSB41AB1 datasheet(13/70 Pages) TI

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TSB41AB1

IEEE 1394a2000 ONEPORT CABLE

TRANSCEIVER/ARBITER

SLLS423I − JUNE 2000 − REVISED MARCH 2005

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued)

TERMINAL

NAME

NUMBER

TYPE

I/O

DESCRIPTION

NAME

PAP

PHP

GQE

ZQE

TYPE

I/O

DESCRIPTION

C4, C6,

C7, D7,

F3, F8,

G3, G4,

G8, H8

F8,

G8,

−

Each of these terminals is not connected to the silicon device.

NC:

Group 1

B4, C5,

D3, D4,

D5, E3,

B4,

D5,

Supply

−

Each of these terminals is not connected to the silicon device, but they

are connected to each other. It is recommended this group of terminals

be used for a via connection to the GND plane in application board.

NC:

Group 2

D6, E5,

E6, E7,

E8, F6,

D6,

E5,

E6,

E8,

Supply

−

Each of these terminals is not connected to the silicon device, but they

are connected to each other. It is recommended this group of terminals

be used for a via connection to the VDD−supply plane in application

board.

NC:

Group 3

F4, F5,

F4,

F5,

Supply

−

Each of these terminals is not connected to the silicon device, but they

are connected to each other. It is recommended this group of terminals

be used for a via connection to the GND plane in application board.

NC:

Group 4

G5, G6,

−

Supply

−

Each of these terminals are not connected to the silicon device, but they

are connected to each other. It is recommended this group of terminals

be used for a via connection to the VDD−supply plane in application

board.

PC0

PC1

PC2

CMOS

Power class programming inputs. On hardware reset, these inputs set

the default value of the power class indicated during self-ID.

Programming is done by tying these terminals high or low. See Table 9

for encoding.

CMOS

Power-down input. A high on this terminal turns off all internal circuitry

except the cable-active monitor circuits, which control the CNA output

(64-terminal PAP package only). Asserting the PD input high also

activates an internal pulldown on the RESET terminal to force a reset of

the internal control logic. (PD is provided for legacy compatibility and is

not recommended for power management in place of IEEE 1394a-2000

suspend/resume LPS and C/LKON features.)

PLLGND

57, 58

A6, B5

A6,

Supply

−

PLL circuit ground terminals. These terminals should be tied together to

the low-impedance circuit board ground plane.

PLLVDD

Supply

−

PLL circuit power terminals. A combination of high-frequency decoupling

capacitors near each terminal is suggested, such as paralleled 0.1

µF

and 0.001

µF. Lower frequency 10-µF filtering capacitors are also

recommended. This supply terminal is separated from DVDD and AVDD

inside the device to provide noise isolation. It should be tied at a

low-impedance point on the circuit board.

Bias

−

Current setting resistor terminals. These terminals are connected

through an external resistor to set the internal operating currents and

cable driver output currents. A resistance of 6.34 k

Ω ±1.0% is required

to meet the IEEE Std 1394-1995 output voltage limits.

NOTE: It is strongly recommended that signals tied to VDD use a 1-kΩ resistor (minimum). Tying signals directly to VCC may result in ESD failures.

Signals tied to ground may be tied directly.

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