PIC16F684 datasheet(68/192 Pages) MICROCHIP

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PIC16F684

DS41202F-page 66

9.1

ADC Configuration

When configuring and using the ADC the following

functions must be considered:

• Port configuration

• Channel selection

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

• Results formatting

9.1.1

PORT CONFIGURATION

The ADC can be used to convert both analog and digital

signals. When converting analog signals, the I/O pin

should be configured for analog by setting the associated

TRIS and ANSEL bits. See the corresponding port

section for more information.

9.1.2

CHANNEL SELECTION

The CHS bits of the ADCON0 register determine which

channel is connected to the sample and hold circuit.

When changing channels, a delay is required before

starting the next conversion. Refer to Section 9.2

“ADC Operation” for more information.

9.1.3

ADC VOLTAGE REFERENCE

The VCFG bit of the ADCON0 register provides control

of the positive voltage reference. The positive voltage

reference can be either VDD or an external voltage

source. The negative voltage reference is always

connected to the ground reference.

9.1.4

CONVERSION CLOCK

The source of the conversion clock is software select-

able via the ADCS bits of the ADCON1 register. There

are seven possible clock options:

•FOSC/2

•FOSC/4

•FOSC/8

•FOSC/16

•FOSC/32

•FOSC/64

•FRC (dedicated internal oscillator)

The time to complete one bit conversion is defined as

TAD. One full 10-bit conversion requires 11 TAD periods

as shown in Figure 9-3.

For correct conversion, the appropriate TAD specification

must be met. See A/D conversion requirements in

Section 15.0 “Electrical Specifications” for more

information. Table 9-1 gives examples of appropriate

ADC clock selections.

TABLE 9-1:

ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)

Note:

Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

Note:

Unless using the FRC, any changes in the

system clock frequency will change the

ADC

clock

frequency,

which

may

adversely affect the ADC result.

ADC Clock Period (TAD)

Device Frequency (FOSC)

ADC Clock Source

ADCS<2:0>

20 MHz

8 MHz

4 MHz

1 MHz

FOSC/2

000

100 ns(2)

250 ns(2)

500 ns(2)

2.0

μs

FOSC/4

100

200 ns(2)

500 ns(2)

1.0

μs(2)

4.0

μs

FOSC/8

001

400 ns(2)

1.0

μs(2)

2.0

μs

8.0

μs(3)

FOSC/16

101

800 ns(2)

2.0

μs4.0 μs

16.0

μs(3)

FOSC/32

010

1.6

μs4.0 μs

8.0

μs(3)

32.0

μs(3)

FOSC/64

110

3.2

μs

8.0

μs(3)

16.0

μs(3)

64.0

μs(3)

FRC

x11

2-6

μs(1,4)

2-6

μs(1,4)

2-6

μs(1,4)

2-6

μs(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1:

The FRC source has a typical TAD time of 4

μs for VDD > 3.0V.

These values violate the minimum required TAD time.

For faster conversion times, the selection of another clock source is recommended.

When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the

conversion will be performed during Sleep.

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