ADAS1000 datasheet(68/80 Pages) AD

68 / 80 page

ADAS1000/ADAS1000-1/ADAS1000-2

Data Sheet

Rev. A | Page 68 of 80

Table 47. Operating State Register (OPSTAT) Address 0x1F, Reset Value = 0x0000001

R/W

Default

Bit

Name

Function

[23:4]

Reserved

Reserved.

Internal error

Internal digital failure. This is set if an error is detected in the digital core.

Configuration status

This bit is set after a reset indicating that the configuration has not been read yet.

Once the configuration is set, this bit is ready.

0 = ready.

1 = busy.

PLL lock

PLL lock lost. This bit is set if the internal PLL loses lock after it is enabled and

locked. This bit is cleared once this register is read or the PWREN bit (Address

0x01[1]) is cleared.

0 = PLL locked.

1 = PLL lost lock.

PLL locked status

This bit indicates the current state of the PLL locked status.

0 = PLL not locked.

1 = PLL locked.

This register is not part of framing data, but can be read by issuing a register read command of this address. This register assists support efforts giving insight into

potential areas of malfunction within a failing device.

Table 48. Extended Switch for Respiration Inputs Register (EXTENDSW) Address 0x20, Reset Value = 0x000000

R/W

Default

Bit

Name

Switch

Function

R/W

EXT_RESP_RA to ECG1_LA

SW1a

External respiration electrode input switch to channel electrode input (see

Figure 69).1

0 = switch open.

1 = switch closed.

EXT_RESP_RA to ECG2_LL

SW1b

EXT_RESP_RA to ECG3_RA

SW1c

EXT_RESP_RA to ECG4_V1

SW1d

EXT_RESP_RA to ECG5_V2

SW1e

EXT_RESP_LL to ECG1_LA

SW2a

EXT_RESP_LL to ECG2_LL

SW2b

EXT_RESP_LL to ECG3_RA

SW2c

EXT_RESP_LL to ECG4_V1

SW2d

EXT_RESP_LL to ECG5_V2

SW2e

EXT_RESP_LA to ECG1_LA

SW3a

EXT_RESP_LA to ECG2_LL

SW3b

EXT_RESP_LA to ECG3_RA

SW3c

EXT_RESP_LA to ECG4_V1

SW3d

EXT_RESP_LA to ECG5_V2

SW3e

R/W

AUX_V1

V1 and V2 electrodes can be used for measurement purposes other than ECG.

To achieve this, they must be disconnected from the patient VCM voltage

provided from the internal common-mode buffer and, instead, connected to

the internal VCM_REF level of 1.3 V.

Setting the AUX_Vx bits high connects the negative input of the V1 channel

amplifier to internal VCM_REF level. This allows the user to make alternative

measurements on V1 relative to the VCM_REF level.

If using digital lead mode, use these bits in conjunction with Bits[6:5]

(NO_MATH_Vx).

R/W

AUX_V2

R/W

NOMATH_V1

In digital lead mode, the digital core always calculates V1’ and V2’ with respect

to WCT (LA + LL + RA)/3.

Where V1 or V2 are used for alternative measurement purposes other than

ECG, this math calculation must be disabled. These bits are most likely used in

conjunction with Bits[8:7] (AUX_Vx).

Set NOMATH_Vx bits high to disable the math calculation in V1 and V2,

respectively.

NOMATH_V2

R/W

[4:0]

Reserved

Reserved, set to 0.

ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these EXT_RESP_xx pins.

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