LP2998 datasheet(16/26 Pages) TI

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VTT

LP2998

PVIN

VDDQ

VREF

AVIN

VREF = 1.25V

VSENSE

GND

47 PF

VDDQ = 2.5V

VDD = 2.5V

VTT = 1.25V

330 PF

0.01 PF

VTT

LP2998

PVIN

VDDQ

VREF

AVIN

VSENSE

GND

CIN

COUT

CREF

AVIN = 2.5V

VDDQ = 1.8V

VTT = 0.9V

VREF = 0.9V

LP2998

SNVS521I – DECEMBER 2007 – REVISED APRIL 2013

www.ti.com

OUTPUT CAPACITOR SELECTION

For applications utilizing the LP2998 to terminate SSTL-2 I/O signals the typical application circuit shown in

Figure 27 can be implemented.

Figure 27. Typical SSTL-2 Application Circuit

This circuit permits termination in a minimum amount of board space and component count. Capacitor selection

can be varied depending on the number of lines terminated and the maximum load transient. However, with

motherboards and other applications where VTT is distributed across a long plane, it is recommended to use

multiple bulk capacitors in addition to high frequency decoupling. Figure 28 depicts an example circuit where 2

bulk output capacitors could be situated at both ends of the VTT plane for optimal placement. Large aluminum

electrolytic capacitors are typically used for their low ESR and low cost.

Figure 28. Typical SSTL-2 Application Circuit for Motherboards

In most PC applications, an extensive amount of decoupling is required because of the long interconnects

encountered with the DDR-SDRAM DIMMs mounted on modules. As a result, bulk aluminum electrolytic

capacitors in the range of 1000uF are typically used.

PCB Layout Considerations

1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin.

2. VSENSE should be connected to the VTT termination bus at the point where regulation is required. For

motherboard applications an ideal location would be at the center of the termination bus.

3. VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides the

most accurate point for creating the reference voltage.

4. For improved thermal performance excessive top side copper should be used to dissipate heat from the

package. Numerous vias from the ground connection to the internal ground plane will help. Additionally these

can be located underneath the package if manufacturing standards permit.

5. Care should be taken when routing the VSENSE trace to avoid noise pickup from switching I/O signals. A

0.1uF ceramic capacitor located close to the SENSE can also be used to filter any unwanted high frequency

signal. This can be an issue especially if long SENSE traces are used.

6. VREF should be bypassed with a 0.01 µF or 0.1 µF ceramic capacitor for improved performance. This

capacitor should be located as close as possible to the VREF pin.

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