TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

16

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

data register, LSB first

D1 in the input data register (LSB first) controls the direction of the output binary data transfer. When D1 is reset

to 0, the conversion result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of

MSB first or LSB first always affects the next I/O cycle and not the current I/O cycle. When changing from one

data direction to another, the current I/O cycle is never disrupted.

data register, bipolar format

D0 (BIP) in the input data register controls the binary data format used to represent the conversion result. When

D0 is cleared to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the

is a code of a one followed by zeros (100 ...0).

When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion

code of all zeros (000 . . . 0). The MSB is interpreted as the sign bit. The bipolar data format is related to the

unipolar format in that the MSBs are always each other’s complement.

Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output

during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the

current I/O cycle is not affected.

EOC output

The EOC signal indicates the beginning and the end of conversion. In the reset state, EOC is always high. During

the sampling period (beginning after the fourth falling edge of the I/O CLOCK sequence), EOC remains high

until the internal sampling switch of the converter is safely opened. The opening of the sampling switch occurs

after the eighth, twelfth, or sixteenth I/O CLOCK falling edge, depending on the data-length selection in the input

data register. After the EOC signal goes low, the analog input signal can be changed without affecting the

conversion result.

The EOC signal goes high again after the conversion is completed and the conversion result is latched into the

output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.

On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When

CS is negated between conversions, the first bit of the current conversion result occurs at DATA OUT on the

falling edge of CS.

data format and pad bits

D3 and D2 of the input data register determine the number of significant bits in the digital output that represent

the conversion result. The LSB-first bit determines the direction of the data transfer while the BIP bit determines

the arithmetic conversion. The numerical data is always justified toward the MSB in any output format.

The internal conversion result is always 12 bits long. When an 8-bit data transfer is selected, the four LSBs of

the internal result are discarded to provide a faster one-byte transfer. When a 12-bit transfer is used, all bits are

transferred. When a 16-bit transfer is used, four LSB pad bits are always appended to the internal conversion

result. In the LSB-first mode, four leading zeros are output. In the MSB-first mode, the last four bits output are

zeros.