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ADL5375ACPZ-R7 датащи(PDF) 32 Page - Analog Devices |
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ADL5375ACPZ-R7 датащи(HTML) 32 Page - Analog Devices |
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32 / 36 page ![]() ADL5375 Data Sheet Rev. C | Page 32 of 36 Figure 76. Evaluation Board Layout, Top Layer Figure 77. Evaluation Board Layout, Bottom Layer Thermal Grounding and Evaluation Board Layout The package for the ADL5375 features an exposed paddle on the underside that should be well soldered to a low thermal and electrical impedance ground plane. This paddle is typically soldered to an exposed opening in the solder mask on the evaluation board. Figure 78 illustrates the dimensions used in the layout of the ADL5375 footprint on the ADL5375 Evaluation Board (1 mil. = 0.0254 mm). Notice the use of nine via holes on the exposed paddle. These ground vias should be connected to all other ground layers on the evaluation board to maximize heat dissipation from the device package. 82 mil. 12 mil. 12 mil. 23 mil. 133.8 mil. 98.4 mil. 19.7 mil. 25 mil. Figure 78. Dimensions for Evaluation Board Layout for the ADL5375 Package Under these conditions, the thermal impedance of the ADL5375 was measured to be approximately 30°C/W in still air. |
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