LTC1865LCMS datasheet(14/24 Pages) LINER

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LTC1864/LTC1865

18645fb

APPLICATIONS INFORMATION

LTC1865 OPERATION

Operating Sequence

The LTC1865 conversion cycle begins with the rising edge

of CONV. After a period equal to tCONV, the conversion is

ﬁnished. If CONV is left high after this time, the LTC1865

goes into sleep mode drawing only leakage current. The

LTC1865’s 2-bit data word is clocked into the SDI input

on the rising edge of SCK after CONV goes low. Additional

inputs on the SDI pin are then ignored until the next CONV

cycle. The shift clock (SCK) synchronizes the data transfer

with each bit being transmitted on the falling SCK edge and

captured on the rising SCK edge in both transmitting and

receiving systems. The data is transmitted and received

simultaneously (full duplex). After completing the data

transfer, if further SCK clocks are applied with CONV low,

SDO will output zeros indeﬁnitely. See Figure 4.

Analog Inputs

The two bits of the input word (SDI) assign the MUX

conﬁguration for the next requested conversion. For a

given channel selection, the converter will measure the

voltage between the two channels indicated by the “+”

and “–” signs in the selected row of the following table. In

single-ended mode, all input channels are measured

with respect to GND. A zero code will occur when the

“+” input minus the “–” input equals zero. Full scale oc-

curs when the “+” input minus the “–” input equals VREF

minus 1LSB. See Figure 5. Both the “+” and “–” inputs

are sampled at the same time so common mode noise

is rejected. The input span in the SO-8 package is ﬁxed

at VREF = VCC. If the “–” input in differential mode is

grounded, a rail-to-rail input span will result on the “+”

input.

Reference Input

The reference input of the LTC1865 SO-8 package is

internally tied to VCC. The span of the A/D converter is

therefore equal to VCC. The voltage on the reference

input of the LTC1865 MSOP package deﬁnes the span

of the A/D converter. The LTC1865 MSOP package can

operate with reference voltages from 1V to VCC.

Figure 4. LTC1865 Operating Sequence

MUX ADDRESS

Table 1. Multiplexer Channel Selection

SGL/DIFF

ODD/SIGN

CHANNEL #

–

GND

–

18645 TBL1

SINGLE-ENDED

MUX MODE

DIFFERENTIAL

MUX MODE

CONV

SDI

SCK

SDO

B15 B14

B12

B10

B0*

Hi-Z

B13

B11

S/D O/S

DON’T CARE

tCONV

18645 F04

SLEEP MODE

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE

APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY

Hi-Z

tSMPL

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