AD6620AS datasheet(17/44 Pages) AD

17 / 44 page

AD6620

–17–

REV. A

tSI

tHI

CLK

IN[15:0]

EXP[2:0]

A/B

BN+1

AN+1

AN+2

BN+2

CLK

IF CLK 2x IS USED TO CLOCK THE AD6620, THE FIRST RISING EDGE AFTER

THE A/B TRANSITION WILL LATCH THE DATA.

Figure 25. Full Rate Input Timing, Diversity Channel Real

Mode

If fractional rate input timing is necessary in the Diversity Chan-

nel Real Mode, the A/B pin must toggle at half the rate of the

A/D sample clock. The timing diagram below shows a 3

× pro-

cessing clock. In this situation there will be one ADC encode

pulse for every three AD6620 CLK pulses and data must be

taken on every third CLK pulse. The CLK edges that corre-

spond to the latching of A and B channel data are shown in

Figure 26.

tSI

tHI

CLK

IN[15:0]

EXP[2:0]

A/B

Figure 26. Fractional Rate Input Timing (3

× CLK), Diversity

Channel Real Mode

Single Channel Complex Mode

In the Single Channel Complex input mode, A/B high identi-

fies the in-phase samples and A/B low identifies quadrature

samples. The quadrature samples are paired with the previous

in-phase samples. The timing for this mode is the same as that

of the Diversity Channel Real Mode. This mode is useful for

accepting complex output data from another AD6620 or another

source to increase filtering and or decimation rates.

In the Single Channel Complex Mode the CIC2 decimation

must be set to two (MCIC2 = 2). This is necessary in order to

allow enough CLK cycles to process the complex input data as

described below.

First clock cycle: (A/B high).

– I data loaded from the input port.

– The I data-path gets I

× cosine.

– The Q data-path gets I

× sine.

– The first integrator of the CIC2 adds these values to its

previous sums.

– The rest of the CIC2 is idle.

Second clock cycle: (A/B low).

– Q data loaded from the input port.

– The I data-path gets Q

× sine.

– The Q data-path gets Q

× cosine.

– The first integrator of the I path of the CIC2 completes the

sum (I

× cosine - Q × sine) and the first integrator of the Q

path of the CIC2 completes the sum j(I

× sine + Q × cosine).

– The rest of the CIC2 operates on these sums, which is the

complete complex multiply. The data is then multiplexed

through the rest of the chip as if it were single channel real data.

Simplified Input Data Port Schematic

Figure 27 details a simplified schematic for the input data port.

The first thing to note is that IN[15:0], EXP[2:0] and A/B are

all synchronously latched with CLK. Note also that upon soft

reset, a seven pipeline delay (sample clock delay) exists in the

data path. This delay is synchronous with CLK, but is in fact

seven valid sample data delays. For instance, in single channel

CLK

LOGIC "1"

SOFT RESET

CLR

ENB

IN[15:0]

EXP[2:0]

A/B

CLK

MULTIPLEXER

DUAL CHANNEL REAL

SINGLE CHANNEL COMPLEX

INT IN[15:0]

INT EXP[2:0]

INT DATA STROBE

CLR

DELAY 7

ENB

SET

CLR

Figure 27. Simplified Input Data Port Schematic for the AD6620

AD6620AS датащи(PDF) 17 Page - Analog Devices

AD6620AS датащи(HTML) 17 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

датащи скачать

ссылки URL