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AD5379ABCZ датащи(PDF) 13 Page - Analog Devices |
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AD5379ABCZ датащи(HTML) 13 Page - Analog Devices |
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13 / 29 page ![]() AD5379 Rev. B | Page 12 of 28 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 456 789 10 11 12 12 3 456 789 10 11 12 A B C D E F G H J K L M A B C D E F G H J K L M AD5379 TOP VIEW Figure 7. Pin Configuration Table 7. 108-Lead CSPBGA Ball Configuration CSPBGA Number Ball Name A1 REG0 A2 VCC3 A3 DB10 A4 AGND4 A5 VBIAS A6 VOUT5 A7 AGND3 A8 REFGNDA1 A9 VDD5 A10 VSS5 A11 VSS4 A12 VDD4 B1 REG1 B2 DGND4 B3 DB9 B4 CLR B5 VOUT7 B6 VOUT6 B7 VOUT0 B8 VOUT1 B9 VOUT2 B10 VOUT31 B11 REFGNDD1 B12 VOUT30 C1 DB13 C2 DB12/SCLK C3 DB11/DIN C4 SER/PAR1 CSPBGA Number Ball Name C5 LDAC C6 VOUT8 C7 VOUT3 C8 VOUT4 C9 VOUT9 C10 VOUT34 C11 VOUT32 C12 VOUT33 D1 DB7 D2 DB8 D3 DGND1 D10 VREF1(−) D11 VOUT35 D12 VOUT36 E1 DB5 E2 DB6 E3 VCC1 E10 REFGNDB2 E11 VOUT37 E12 VOUT38 F1 DB4 F2 DB3 F3 DB2 F10 VDD3 F11 REFGNDD2 F12 VOUT39 G1 DB1 G2 DB0 CSPBGA Number Ball Name G3 BUSY G10 VSS3 G11 VOUT29 G12 REFGNDC2 H1 WR/DCEN H2 SDO2 H3 CS/SYNC H10 VOUT28 H11 VOUT26 H12 VOUT27 J1 A0 J2 A1 J3 A2 J10 VOUT19 J11 VOUT24 J12 VOUT25 K1 A4 K2 A5 K3 A3 K4 DGND2 K5 REFGNDA2 K6 VREF2(−) K7 VOUT12 K8 VOUT13 K9 VOUT16 K10 VOUT18 K11 VOUT22 CSPBGA Number Ball Name K12 VOUT23 L1 A7 L2 A6 L3 N/C3 L4 RESET2 L5 VOUT17 L6 AGND2 L7 VOUT14 L8 VOUT10 L9 VDD1 L10 VREF2(+) L11 VOUT20 L12 VOUT21 M1 DGND3 M2 VCC2 M3 FIFOEN1 M4 AGND1 M5 VOUT15 M6 VOUT11 M7 REFGNDB1 M8 VREF1(+) M9 VSS1 M10 VSS2 M11 VDD2 M12 REFGNDC1 1 An internal 1 MΩ pull-down device is located on this logic input; therefore, it can be left floating and defaults to a logic low condition. 2 An internal 1 MΩ pull-up device is located on this logic input; therefore, it can be left floating and defaults to a logic high condition. 3 N/C—Do not connect to this pin. Internal active pull-up device on these logic inputs. They default to a logic high condition. |
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