ADV202 datasheet(13/40 Pages) AD

номер детали	ADV202

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Data Sheet

ADV202

Rev. D | Page 13 of 40

EXTERNAL DMA MODE—FIFO WRITE, BURST MODE

Table 8.

Parameter

Description

Min

Typ

Max

Unit

DREQPULSE

DREQ Pulse Width1

JCLK2 cycles

DREQRTN

WE to DREQ Deassert (DR × Pulse = 0)

2.5

3.5 × JCLK + 7.5 ns

JCLK cycles

DACKSU

DACK to WE Setup

Data Setup

2.5

Data Hold

WELO

WE Assert Pulse Width

1.5

JCLK cycles

WEHI

WE Deassert Pulse Width

1.5

JCLK cycles

DREQWAIT

Last Burst Access to Next DREQ

2.5

4.5 × JCLK + 7.5 ns3

JCLK cycles

1 Applies to assigned DMA channel, if EDMOD0 or EDMOD1[14:11] is programmed to a value that is not 0. Pulse width depends on the value programmed.

2 For a definition of JCLK, see the PLL section.

3 If sufficient space is available in FIFO.

DREQ

DACK

HDATA

WEHI

WELO

tDACKSU

tHD

tSU

tDREQWAIT

DREQPULSE

Figure 13. Burst Write Cycle for DREQ/DMA Mode for Assigned DMA Channel

(EDMOD0/EDMOD1[14:11] NOT Programmed to a Value of 0000)

DREQ

DACK

HDATA

WEHI

WELO

tDACKSU

tHD

tSU

tDREQWAIT

tDREQRTN

Figure 14. Burst Write Cycle for DREQ/DMA Mode for Assigned DMA Channel

(EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000)

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