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Data Sheet

AD9523

Rev. C | Page 13 of 60

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

LDO_PLL1

VDD3_PLL1

REFA

REFB

LF1_EXT_CAP

OSC_CTRL

OSC_IN

LF2_EXT_CAP

LDO_PLL2

VDD3_PLL2

LDO_VCO

REF_SEL

SYNC

VDD3_REF

VDD1.8_OUT[4:5]

OUT4

VDD3_OUT[4:5]

OUT5

VDD1.8_OUT[6:7]

OUT6

VDD3_OUT[6:7]

OUT7

VDD1.8_OUT[8:9]

OUT8

VDD3_OUT[8:9]

OUT9

PIN 1

INDICATOR

AD9523

(TOP VIEW)

NOTES

1. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THESE PINS TO GROUND.

AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT.

ON EXISTING PCB DESIGNS, IT ISACCEPTABLE TO LEAVE PIN 69 CONNECTED TO 1.8V SUPPLY.

2. THE EXPOSED PADDLE IS THE GROUND CONNECTION ON THE CHIP. IT MUST BE

SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY

AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.

Figure 2. Pin Configuration

Table 19. Pin Function Descriptions

No.

Mnemonic

Type1

Description

LDO_PLL1

P/O

1.8 V Internal LDO Regulator Decoupling Pin for PLL1. Connect a 0.47 μF decoupling capacitor from

this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed in

close proximity to the device.

VDD3_PLL1

3.3 V Supply PLL1. Use the same supply as VCXO.

REFA

Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference.

Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

REFA

Complementary Reference Clock Input A. Along with REFA, this pin is the differential input for the

PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3V CMOS input.

REFB

Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference.

Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

REFB

Complementary Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL

reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

LF1_EXT_CAP

PLL1 External Loop Filter Capacitor. Connect a loop filter capacitor to this pin and to ground.

OSC_CTRL

Oscillator Control Voltage. Connect this pin to the voltage control pin of the external oscillator.

OSC_IN

PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the PLL reference.

Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

OSC_IN

Complementary PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the PLL

reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

LF2_EXT_CAP

PLL2 External Loop Filter Capacitor Connection. Connect a capacitor to this pin and LDO_VCO.

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