VIPER37LE datasheet(27/35 Pages) STMICROELECTRONICS

27 / 35 page

VIPER37

Operation description

Doc ID 022218 Rev 1

27/35

After the startup time, tSS, during which the feedback voltage is fixed at VFBlin, the output

capacitor may not be at its nominal value and the controller interprets this situation as an

overload condition. In this case, the OLP delay helps to avoid an incorrect device shutdown

during the startup phase.

Owing to the above considerations, the OLP delay time must be long enough to bypass the

initial output voltage transient and check the overload condition only when the output voltage

is in steady-state. The output transient time depends on the value of the output capacitor

and on the load.

When the value of the CFB capacitor calculated for the loop stability is too low and cannot

ensure enough OLP delay, an alternative compensation network can be used, shown in

Figure 31.

Using this alternative compensation network, two poles (fPFB, fPFB1) and one zero (fZFB) are

introduced by the capacitors CFB and CFB1 and the resistor RFB1.

The capacitor CFB introduces a pole (fPFB) at a higher frequency than fZB and fPFB1. This

pole is usually used to compensate the high frequency zero due to the ESR (equivalent

series resistor) of the output capacitance of the flyback converter.

The mathematical expressions of these poles and zero frequency, considering the scheme

Figure 31, are reported by the equations below:

Equation 6

Equation 7

Equation 8

RFB(DYN) is the dynamic resistance seen by the FB pin.

The CFB1 capacitor fixes the OLP delay and usually CFB1 results much higher than CFB.

Equation 5 can still be used to calculate the OLP delay time but CFB1 must be considered

instead of CFB. Using the alternative compensation network, the user can satisfy, in all

cases, the loop stability and the correct OLP delay time alike.

ZFB

⋅

()

)

DYN

(

)

DYN

(

PFB

⋅

()

)

DYN

(

PFB

⋅

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