AD9773-EB datasheet(21/60 Pages) AD

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AD9773

Rev. D | Page 21 of 60

Address 03h

Bit 7:

Allows the data rate clock (divided down from the DAC

clock) to be output at either the DATACLK pin (Pin 8) or at the

SPI_SDO pin (Pin 53). The default of 0 in this bit enables the

data rate clock at DATACLK, while a 1 in this bit causes the data

rate clock to be output at SPI_SDO. For more information, see

the Two-Port Data Input Mode section.

Bit 1 and Bit 0:

Setting this divide ratio to a higher number

allows the VCO in the PLL to run at a high rate (for best perform-

ance), while the DAC input and output clocks run substantially

slower. The divider ratio is set according to Table 12.

Table 12.

÷1

÷2

÷4

÷8

Address 04h

Bit 7:

Logic 0 (default) disables the internal PLL. Logic 1

enables the PLL.

Bit 6:

Logic 0 (default) sets the charge pump control to

automatic. In this mode, the charge pump bias current is

controlled by the divider ratio defined in Address 03h, Bits 1

and 0. Logic 1 allows the user to manually define the charge

pump bias current using Address 04h, Bits 2, 1, and 0. Adjusting

the charge pump bias current allows the user to optimize the

noise/settling performance of the PLL.

Bit 2, Bit 1, and Bit 0

: With the charge pump control set to

manual, these bits define the charge pump bias current

according to Table 13.

Table 13.

000

50 μA

001

100 μA

010

200 μA

011

400 μA

111

800 μA

Address 05h, 09h

Bit 7, Bit 6, Bit 5, Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0:

These bits

represent an 8-bit binary number (Bit 7 MSB) that defines the

fine gain adjustment of the I (05h) and Q (09h) DAC according

to Equation 1.

Address 06h, 0Ah

Bit 3, Bit 2, Bit 1, and Bit 0:

These bits represent a 4-bit binary

number (Bit 3 MSB) that defines the coarse gain adjustment of

the I (06h) and Q (0Ah) DACs according to Equation 1.

Address 07h, 0Bh

Bit 7, Bit 6, Bit 5, Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0:

These bits

are used in conjunction with Address 08h, Address 0Ch, Bits [1:0].

Address 08h, 0Ch

Bit 1 and Bit 0:

The 10 bits from these two address pairs (07h,

08h and 0Bh, 0Ch) represent a 10-bit binary number that

defines the offset adjustment of the I and Q DACs according to

Equation 1: (07h, 0Bh: Bit 7 MSB; 08h, 0Ch: Bit 0 LSB).

Address 08h, 0Ch

Bit 7:

This bit determines the direction of the offset of the I (08h)

and Q (0Ch) DACs. A Logic 0 applies a positive offset current to

IOUTA, while a Logic 1 applies a positive offset current to IOUTB.

The magnitude of the offset current is defined by the bits in

Addresses 07h, 0Bh, 08h, and 0Ch according to Equation 1.

Equation 1 shows IOUTA and IOUTB as a function of fine gain,

coarse gain, and offset adjustment when using 2R mode. In 1R

mode, the current IREF is created by a single FSADJ1 resistor

(Pin 60). This current is divided equally into each channel so

that a scaling factor of one-half must be added to these

equations for full-scale currents for both DACs and the offset.

)

(

1024

)

(

1024

256

)

(

1024

256

OFFSET

DATA

FINE

COARSE

DATA

FINE

COARSE

REF

OFFSET

REF

OUTB

REF

OUTA

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(1)

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