AD9822

Rev. B | Page 13 of 20

INTERNAL REGISTER DESCRIPTIONS

Table 6. Internal Register Map

Register Name

Address

Data Bits

A2

A1

A0

D8

D7

D6

D

D4

D3

D2

D1

D0

Configuration

0

0

0

0

0

VREF

3Ch/1Ch

CDS On

Clamp

Pwr Dn

0

0

MUX

0

0

1

0

RGB/BGR

Red

Green

Blue

0

0

0

0

Red PGA

0

1

0

0

0

0

MSB

LSB

Green PGA

0

1

1

0

0

0

MSB

LSB

Blue PGA

1

0

0

0

0

0

MSB

LSB

Red Offset

1

0

1

MSB

LSB

Green Offset

1

1

0

MSB

LSB

Blue Offset

1

1

1

MSB

LSB

Configuration Register

The Configuration Register controls the AD9822’s operating mode and bias levels. Bits D8, D1, and D0 should always be set low. Bit D7

sets the full-scale voltage range of the AD9822’s ADC to either 4 V (high) or 2 V (low). Bit D6 controls the internal voltage reference. If the

AD9822’s internal voltage reference is used, this bit is set high. Setting Bit D6 low disables the internal voltage reference, allowing an

external voltage reference to be used. Bit D5 configures the AD9822 for either the 3-channel (high) or 1-channel (low) mode of operation.

Setting Bit D4 high enables the CDS mode of operation and setting this bit low enables the SHA mode of operation. Bit D3 sets the dc bias

level of the AD9822’s input clamp. This bit should always be set high for the 4 V clamp bias, unless a CCD with a reset feedthrough

transient exceeding 2 V is used. If the 3 V clamp bias level is used, the peak-to-peak input signal range to the AD9822 is reduced to 3 V

maximum. Bit D2 controls the power-down mode. Setting Bit D2 high places the AD9822 into a very low power “sleep” mode. All register

contents are retained while the AD9822 is in the power-down state.

Table 7. Configuration Register Settings

D8

D7

D6

D5

D4

D3

D2

D1

D0

Set to 0

Set to 0

Internal VREF

No. of Channels

CDS Operation

Input Clamp Bias

Power-Down

Set to 0

Set to 0

1 = Enabled1

1 = 3-Ch Mode1

1 = CDS Mode1

1 = 4 V1

1 = On

0 = Disabled

0 = 1-Ch Mode

0 = SHA Mode

0 = 3 V

0 = Off (Normal)1

MUX Register

The MUX register controls the sampling channel order in the AD9822. Bits D8, D3, D2, D1, and D0 should always be set low. Bit D7 is

used when operating in 3-channel mode. Setting Bit D7 high sequences the MUX to sample the red channel first, then the green channel,

and then the blue channel. When in this mode, the CDSCLK2 pulse always resets the MUX to sample the red channel first (see Figure 3).

When Bit D7 is set low, the channel order is reversed to blue first, green second, and red third. The CDSCLK2 pulse always resets the

MUX to sample the blue channel first. Bits D6, D5, and D4 are used when operating in 1-channel mode. Bit D6 is set high to sample the

red channel. Bit D5 is set high to sample the green channel. Bit D4 is set high to sample the blue channel. The MUX remains stationary

during 1-channel mode.

Table 8. MUX Register Settings

D8

D7

D6

D5

D4

D3

D2

D1

D0

Set to 0

3-Channel Select

1-Channel Select

1-Channel Select

1-Channel Select

Set to 0

Set to 0

Set to 0

Set to 0

1 = R-G-B1

1 = RED1

1 = GREEN

1 = BLUE

0 = B-G-R

0 = Off

0 = Off1

0 = Off1