AD7836

–5–

REV. A

PIN DESCRIPTION

Pin Mnemonic

Description

Logic Power Supply; +5 V

± 5%.

Negative Analog Power Supply; –15 V

± 5%.

Positive Analog Power Supply; +15 V

± 5%.

DGND

Digital Ground.

AGND

Analog Ground.

Reference Inputs for DAC A. These reference voltages are referred to AGND.

Reference Inputs for DAC B. These reference voltages are referred to AGND.

Reference Inputs for DAC C. These reference voltages are referred to AGND.

Reference Inputs for DAC D. These reference voltages are referred to AGND.

DAC Outputs.

CS

Level-Triggered Chip Select Input (active low). The device is selected when this input is low.

DB0 . . . DB13

Parallel Data Inputs. The AD7836 can accept a straight 14-bit parallel word on DB0 to DB13 where

DB13 is the MSB and DB0 is the LSB.

A0, A1, A2

Address inputs. A0, A1 and A2 are decoded to select one of the five input latches for a data transfer.

CLR

Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog outputs are

switched to the externally set potential on the DUTGND pin. The contents of data registers A to E are

not affected when the CLR pin is taken low. When CLR is brought back high, the DAC outputs revert

back to their original outputs as determined by the data in their data registers.

WR

Level-Triggered Write Input (active low), when active and used in conjunction with CS to write data to

the AD7836 input buffer. Data is latched into the selected data register on the rising edge of WR.

DUTGND A

Device Sense Ground for DAC A. Vout A is referenced to the voltage applied to this pin.

DUTGND B

Device Sense Ground for DAC B. Vout B is referenced to the voltage applied to this pin.

DUTGND C

Device Sense Ground for DAC C. Vout C is referenced to the voltage applied to this pin.

DUTGND D

Device Sense Ground for DAC D. Vout D is referenced to the voltage applied to this pin.

SEL

Select pin, active high level triggered input. When the SEL input is high, the user programmed value in

DATAREG E will be loaded into all DAC registers and the DAC outputs updated accordingly. The con-

tents of the other DATA REGs (A–D) will not be affected by the SEL pin.

PIN CONFIGURATION

12

13

14

15

16

17

18

19

21

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

AD7836

NC = NO CONNECT

20

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

1

23

456789

10 11

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DGND

CLR

AGND

NC

NC