PCA9535E, PCA9535EC

http://onsemi.com

2

BLOCK DIAGRAM

Remark: All I/Os are set as inputs at reset.

Figure 1. Block Diagram

PCA9535E

POWER−ON

RESET

CONTROL

INPUT

FILTER

SCL

SDA

INPUT/

OUTPUT

PORTS

IO0_0

8−bit

write pulse

read pulse

IO0_2

IO0_1

IO0_3

IO0_4

IO0_5

IO0_6

IO0_7

INPUT/

OUTPUT

PORTS

IO1_0

8−bit

write pulse

read pulse

IO1_2

IO1_1

IO1_3

IO1_4

IO1_5

IO1_6

IO1_7

INT

AD1

AD0

AD2

LP filter

PCA9535EC

1. PCA9535EC I/Os are open−drain only. The portion of the PCA9535E schematic marked inside the dotted line box is not in

PCA9535EC.

Figure 2. Simplified Schematic of I/Os

At power−on reset, all registers return to default values.

I/O pin

output port

register data

configuration

register

DQ

CK

Q

data from

shift register

write

configuration

pulse

output port

register

DQ

CK

write pulse

polarity inversion

register

DQ

CK

data from

shift register

write polarity

pulse

input port

register

DQ

CK

read pulse

input port

register data

polarity

inversion

register data

FF

data from

shift register

FF

FF

FF

Q1

Q2

to INT

(1)